Code generation based on trellis diagrams. - Bernhard Wess (Code Generation for Embedded Processors, 1994)

Cooperative register assignment and code compaction for digital signal processors with irregular datapaths. - Werner Kreuzer; Bernhard Wess (ICASSP, 1997)

Constructing memory layouts for address generation units supporting offset 2 access. - Bernhard Wess; Martin Gotschlich (ICASSP, 1997)

Minimization of data address computation overhead in DSP programs. - Bernhard Wess; Martin Gotschlich (ICASSP, 1998)

Operation scheduling for parallel functional units using genetic algorithms. - Thomas Zeitlhofer; Bernhard Wess (ICASSP, 1999)

Dynamic trellis diagrams for optimized DSP code generation. - Stefan Fröhlich; Martin Gotschlich; Udo Krebelder; Bernhard Wess (ISCAS (3), 1999)

Minimization of Data Address Computation Overhead in DSP Programs. - Bernhard Wess (Des. Autom. Embed. Syst., 1999)

Simulated evolutionary code generation for heterogeneous memory-register DSP-architectures. - Bernhard Wess (EUSIPCO, 2000)

Optimum register assignment for heterogeneous register-set architectures. - Thomas Zeitlhofer; Bernhard Wess (ISCAS (3), 2003)

List-coloring of interval graphs with application to register assignment for heterogeneous register-set architectures. - Thomas Zeitlhofer; Bernhard Wess (Signal Process., 2003)

Optimum address pointer assignment for digital signal processors. - Bernhard Wess; Thomas Zeitlhofer (ICASSP (5), 2004)

A comparison of graph coloring heuristics for register allocation based on coalescing in interval graphs. - Thomas Zeitlhofer; Bernhard Wess (ISCAS (4), 2004)

On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment. - Bernhard Wess; Thomas Zeitlhofer (SCOPES, 2004)

Integrated assignment of registers and functional units for heterogeneous vliw-architectures. - Thomas Zeitlhofer; Bernhard Wess (SoCC, 2005)

Design Methods for DSP Systems. - Markus Rupp; Bernhard Wess; Shuvra S. Bhattacharyya (EURASIP J. Adv. Signal Process., 2006)