Infrastructure IP for Back-End Yield Improvement. - L. Forli; Jean-Michel Portal; Didier Née; Bertrand Borot (ITC, 2003)

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. - Manuel Sellier; Jean-Michel Portal; Bertrand Borot; Steve Colquhoun; Richard Ferrant; Frédéric Boeuf; Alexis Farcy (ISQED, 2008)

A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter. - Brice Lhomme; Yann Carminati; Bertrand Borot; Olivier Callen; Thierry Burdeau; Sylvain Clerc (ESSCIRC, 2010)

Back-end soft and hard defect monitoring using a single test chip. - Fabrice Rigaud; Jean-Michel Portal; Hassen Aziza; Didier Née; Julien Vast; Fabrice Argoud; Bertrand Borot (Microelectron. Reliab., 2011)