Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. - Bertrand Folco; Vivian Brégier; Laurent Fesquet; Marc Renaudin (VLSI-SoC, 2005)

State-holding in Look-Up Tables: application to asynchronous logic. - Laurent Fesquet; Bertrand Folco; Mathieu Steiner; Marc Renaudin (VLSI-SoC, 2006)