Reed-Solomon behavioral virtual component for communication systems. - Emmanuel Casseau; Bertrand Le Gal; Christophe Jégo; Nathalie Le Heno; Eric Martin 001 (ISCAS (4), 2004)

Hardware Virtual Components Compliant with Communication System Standards. - Nabil Abdelli; Pierre Bomel; Emmanuel Casseau; Anne-Marie Fouilliart; Christophe Jégo; Philippe Kajfasz; Bertrand Le Gal; Nathalie Le Heno (DSD, 2005)

C-based rapid prototyping for digital signal processing. - Emmanuel Casseau; Bertrand Le Gal; Pierre Bomel; Christophe Jégo; Sylvain Huet; Eric Martin 001 (EUSIPCO, 2005)

Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. - Bertrand Le Gal; Emmanuel Casseau; Eric Martin 001 (EUSIPCO, 2005)

Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. - Bertrand Le Gal; Emmanuel Casseau; Sylvain Huet; Eric Martin 001 (ISVLSI, 2005)

IP Generation Targeting Multiple Bit-Width Standards. - Bertrand Le Gal; Emmanuel Casseau (ICECS, 2006)

Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. - Caaliph Andriamisaina; Bertrand Le Gal; Emmanuel Casseau (SiPS, 2006)

Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems. - Bertrand Le Gal; Caaliph Andriamisaina; Emmanuel Casseau (SoCC, 2006)

Mathematical functions based watermarking for IPP. - Bertrand Le Gal; Lilian Bossuet; Dominique Dallet (ICECS, 2007)

HLS design flow for the synthesis of multimode systems under multiple constraints. - Bertrand Le Gal; Lilian Bossuet; Shafqat Khan; Emmanuel Casseau (ICECS, 2007)

Orthogonal correction implementation for time interleaved analog-to-digital converters: Realtime application. - Guillaume Ferré; Bertrand Le Gal; Lilian Bossuet; Maher Jridi; Dominique Dallet; Pierre Colucci (EUSIPCO, 2008)

A new orthogonal online digital calibration for time-interleaved analog-to-digital converters. - Guillaume Ferré; Maher Jridi; Lilian Bossuet; Bertrand Le Gal; Dominique Dallet (ISCAS, 2008)

Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. - Bertrand Le Gal; Emmanuel Casseau; Caaliph Andriamisaina (Tech. Sci. Informatiques, 2008)

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. - Bertrand Le Gal; Emmanuel Casseau; Sylvain Huet (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Automated multimode system design for high performance DSP applications. - Bertrand Le Gal; Emmanuel Casseau (EUSIPCO, 2009)

Experiments on designing low power decimation filter for multistandard receiver on heterogeneous targets. - Nadia Khouja; Bertrand Le Gal; Khaled Grati; Adel Ghazel (EUSIPCO, 2009)

High-level synthesis for the design of FPGA-based signal processing systems. - Emmanuel Casseau; Bertrand Le Gal (ICSAMOS, 2009)

Design and implementation of a reconfigurable decimation and channel selection filter for GSM and UMTS radio standards. - Nadia Khouja; Khaled Grati; Adel Ghazel; Bertrand Le Gal (WCNC, 2009)

Area optimization of ROM-based controllers dedicated to digital signal processing applications. - Bertrand Le Gal; Aurélien Ribon; Lilian Bossuet; Dominique Dallet (EUSIPCO, 2010)

A low-area filter bank design methodology for on-chip ADC testing. - Nicolas Mechouk; Dominique Dallet; Lilian Bossuet; Bertrand Le Gal (ICECS, 2010)

Reducing and smoothing power consumption of ROM-based controller implementations. - Bertrand Le Gal; Aurélien Ribon; Lilian Bossuet; Dominique Dallet (SBCCI, 2010)

Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios. - Michael Grand; Lilian Bossuet; Bertrand Le Gal; Guy Gogniat; Dominique Dallet (ARC, 2011)

Assertion support in high-level synthesis design flow. - Aurélien Ribon; Bertrand Le Gal; Christophe Jégo; Dominique Dallet (FDL, 2011)

A system aproach for reducing power consumption of multimedia devices with a low QoE impact. - Willy Aubry; Bertrand Le Gal; Dominique Dallet; Simon Desfarges; Daniel Négru (ICECS, 2011)

A Reconfigurable Multi-core Cryptoprocessor for Multi-channel Communication Systems. - Michael Grand; Lilian Bossuet; Guy Gogniat; Bertrand Le Gal; Jean-Philippe Delahaye; Dominique Dallet (IPDPS Workshops, 2011)

FPGA technology and parallel computing towards automatic microarray image processing. - Bogdan Belean; Monica Borda; Bertrand Le Gal; Raul Malutan (TSP, 2011)

Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. - Bertrand Le Gal; Emmanuel Casseau (EURASIP J. Adv. Signal Process., 2011)

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. - Bertrand Le Gal; Emmanuel Casseau (J. Signal Process. Syst., 2011)

A generic video adaptation FPGA implementation towards content- and context-awareness in future networks. - Willy Aubry; Bertrand Le Gal; Daniel Négru; Simon Desfarges; Dominique Dallet (DASIP, 2012)

FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard. - Bertrand Le Gal; Christophe Jégo (DASIP, 2012)

A generic video adaptation framework towards content-and context-awareness in future networks. - Willy Aubry; Daniel Négru; Bertrand Le Gal; Simon Desfarges; Dominique Dallet (EUSIPCO, 2012)

New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitter. - W. Sanaa; Bertrand Le Gal; Dominique Dallet; Chiheb Rebai; Nathalie Deltimple; Didier Belot; Eric Kerherve (NEWCAS, 2012)

Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards. - Bertrand Le Gal; Christophe Jégo (SiPS, 2012)

Spatial downsizing impact in the transrating tradeoff for content/context awareness in media network. - Willy Aubry; Daniel Négru; Bertrand Le Gal; Dominique Dallet (TEMU, 2012)

FPGA based system for automatic cDNA microarray image processing. - Bogdan Belean; Monica Borda; Bertrand Le Gal; Romulus Terebes (Comput. Medical Imaging Graph., 2012)

Automatic low-cost IP watermarking technique based on output mark insertions. - Bertrand Le Gal; Lilian Bossuet (Des. Autom. Embed. Syst., 2012)

Zebra: Building Efficient Network Message Parsers for Embedded Systems. - Julien Mercadal; Laurent Réveillère; Yérom-David Bromberg; Bertrand Le Gal; Tegawendé F. Bissyandé; Jigar Solanki (IEEE Embed. Syst. Lett., 2012)

Design of multi-mode application-specific cores based on high-level synthesis. - Emmanuel Casseau; Bertrand Le Gal (Integr., 2012)

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers. - Khaled Grati; Nadia Khouja; Bertrand Le Gal; Adel Ghazel (VLSI Design, 2012)

Study and analysis of a new implementation of a mixed-signal cartesian feedback for a low power zero-IF WCDMA transmitter. - A. Aulery; Dominique Dallet; Bertrand Le Gal; Nathalie Deltimple; Didier Belot; Eric Kerherve (NEWCAS, 2013)

Improving the performance of message parsers for embedded systems. - Jigar Solanki; Laurent Réveillère; Yérom-David Bromberg; Bertrand Le Gal; Tegawendé F. Bissyandé (SAC, 2013)

Softcore Processor Optimization According to Real-Application Requirements. - Bertrand Le Gal; Christophe Jégo (IEEE Embed. Syst. Lett., 2013)

Design space exploration for partially reconfigurable architectures in real-time systems. - François Duhem; Fabrice Muller; Willy Aubry; Bertrand Le Gal; Daniel Négru; Philippe Lorenzini (J. Syst. Archit., 2013)

Méthodologie d'optimisation des processeurs embarqués. Une approche favorisant la réduction de la surface et de la consommation des processeurs embarqués. - Bertrand Le Gal; Christophe Jégo (Tech. Sci. Informatiques, 2013)

A Very High Throughput Deblocking Filter for H.264/AVC. - Moez Kthiri; Bertrand Le Gal; Patrice Kadionik; Ahmed Ben Atitallah (J. Signal Process. Syst., 2013)

Software polar decoder on an embedded processor. - Bertrand Le Gal; Camille Leroux; Christophe Jégo (SiPS, 2014)

A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices. - Bertrand Le Gal; Christophe Jégo; Jérémie Crenne (IEEE Embed. Syst. Lett., 2014)

GPU-like on-chip system for decoding LDPC codes. - Bertrand Le Gal; Christophe Jégo (ACM Trans. Embed. Comput. Syst., 2014)

A Flexible NISC-Based LDPC Decoder. - Bertrand Le Gal; Christophe Jégo; Camille Leroux (IEEE Trans. Signal Process., 2014)

Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation. - Imen Debbabi; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (ICECS, 2015)

An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes. - Adrien Cassagne; Bertrand Le Gal; Camille Leroux; Olivier Aumage; Denis Barthou (LCPC, 2015)

High-Throughput LDPC Decoder on Low-Power Embedded Processors. - Bertrand Le Gal; Christophe Jégo (IEEE Commun. Lett., 2015)

Multi-Gb/s Software Decoding of Polar Codes. - Bertrand Le Gal; Camille Leroux; Christophe Jégo (IEEE Trans. Signal Process., 2015)

Hardware architecture for lowering the error floor of LTE turbo codes. - Thibaud Tonnellier; Camille Leroux; Bertrand Le Gal; Christophe Jégo; Benjamin Gadat; Nicolas Van Wambeke (DASIP, 2016)

Energy consumption analysis of software polar decoders on low power processors. - Adrien Cassagne; Olivier Aumage; Camille Leroux; Denis Barthou; Bertrand Le Gal (EUSIPCO, 2016)

Multicore implementation of LDPC decoders based on ADMM algorithm. - Imen Debbabi; Nadia Khouja; Fethi Tlili; Bertrand Le Gal; Christophe Jégo (ICASSP, 2016)

Memory reduction techniques for successive cancellation decoding of polar codes. - Bertrand Le Gal; Camille Leroux; Christophe Jégo (ICASSP, 2016)

A scalable 3-phase polar decoder. - Bertrand Le Gal; Camille Leroux; Christophe Jégo (ISCAS, 2016)

Beyond Gbps Turbo decoder on multi-core CPUs. - Adrien Cassagne; Thibaud Tonnellier; Camille Leroux; Bertrand Le Gal; Olivier Aumage; Denis Barthou (ISTC, 2016)

Comparison of different schedulings for the ADMM based LDPC decoding. - Imen Debbabi; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (ISTC, 2016)

Lowering the error floor of double-binary turbo codes: The flip and check algorithm. - Thibaud Tonnellier; Camille Leroux; Bertrand Le Gal; Christophe Jégo; Benjamin Gadat; Nicolas Van Wambeke (ISTC, 2016)

Evaluation of the hardware complexity of the ADMM approach for LDPC decoding. - Imen Debbabi; Nadia Khouja; Fethi Tlili; Bertrand Le Gal; Christophe Jégo (WCNC, 2016)

Fast Converging ADMM-Penalized Algorithm for LDPC Decoding. - Imen Debbabi; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (IEEE Commun. Lett., 2016)

High-Throughput Multi-Core LDPC Decoders Based on x86 Processor. - Bertrand Le Gal; Christophe Jégo (IEEE Trans. Parallel Distributed Syst., 2016)

A Flexible SoC and Its Methodology for Parser-Based Applications. - Bertrand Le Gal; Yérom-David Bromberg; Laurent Réveillère; Jigar Solanki (ACM Trans. Reconfigurable Technol. Syst., 2016)

Real Time LP Decoding of LDPC Codes for High Correction Performance Applications. - Imen Debbabi; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (IEEE Wirel. Commun. Lett., 2016)

Lowering the Error Floor of Turbo Codes With CRC Verification. - Thibaud Tonnellier; Camille Leroux; Bertrand Le Gal; Benjamin Gadat; Christophe Jégo; Nicolas Van Wambeke (IEEE Wirel. Commun. Lett., 2016)

An LP-based algorithm for decoding terminated LDPC convolutional codes. - Hayfa Ben Thameur; Nadia Khouja; Fethi Tlili; Bertrand Le Gal; Christophe Jégo (IINTEC, 2017)

A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures. - Hayfa Ben Thameur; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (ISCC, 2017)

Low-latency software LDPC decoders for x86 multi-core devices. - Bertrand Le Gal; Christophe Jégo (SiPS, 2017)

Successive cancellation decoder for very long polar codes. - Bertrand Le Gal; Camille Leroux; Christophe Jégo (SiPS, 2017)

Reduced complexity ADMM-based schedules for LP decoding of LDPC convolutional codes. - Hayfa Ben Thameur; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (SiPS, 2017)

Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes. - Hayfa Ben Thameur; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (SoftCOM, 2017)

From multicore LDPC decoder implementations to FPGA decoder architectures: a case study. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (ICECS, 2018)

Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (ICECS, 2018)

A scalable and efficient digital signal processing system for real time biological spike detection. - Safouane Noubir; Yannick Bornat; Bertrand Le Gal (ICECS, 2018)

Hardware design of Euclidean Projection modules for ADMM LDPC decoding. - Hayfa Ben Thameur; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (ICECS, 2018)

Model-based Design of Efficient LDPC Decoder Architectures. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (ISTC, 2018)

High data rate and flexible hardware QC-LDPC decoder for satellite optical communications. - Vincent Pignoly; Bertrand Le Gal; Christophe Jégo; Benjamin Gadat (ISTC, 2018)

ADMM hardware decoder for regular LDPC codes using a NISC-based architecture. - Imen Debbabi; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (WCNC, 2018)

Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes. - Hayfa Ben Thameur; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (WCNC, 2018)

High-performance software implementations of SCAN decoder for polar codes. - Bertrand Le Gal; Camille Leroux; Christophe Jégo (Ann. des Télécommunications, 2018)

Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding. - Imen Debbabi; Bertrand Le Gal; Nadia Khouja; Fethi Tlili; Christophe Jégo (J. Signal Process. Syst., 2018)

Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (SiPS, 2019)

AFF3CT: A Fast Forward Error Correction Toolbox! - Adrien Cassagne; Olivier Hartmann; Mathieu Léonardon; Kun He; Camille Leroux; Romain Tajan; Olivier Aumage; Denis Barthou; Thibaud Tonnellier; Vincent Pignoly; Bertrand Le Gal; Christophe Jégo (SoftwareX, 2019)

Fair comparison of hardware and software LDPC decoder implementations for SDR space links. - Vincent Pignoly; Bertrand Le Gal; Christophe Jégo; Benjamin Gadat; Lyonel Barthe (ICECS, 2020)

High speed LDPC decoding for optical space link. - Vincent Pignoly; Bertrand Le Gal; Christophe Jégo; Benjamin Gadat; Lyonel Barthe (ICECS, 2020)

Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding. - Bertrand Le Gal; Yann Delomier; Camille Leroux; Christophe Jégo (SiPS, 2020)

Low-latency and high-throughput software turbo decoders on multi-core architectures. - Bertrand Le Gal; Christophe Jégo (Ann. des Télécommunications, 2020)

Model-based Design of Hardware SC Polar Decoders for FPGAs. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (ACM Trans. Reconfigurable Technol. Syst., 2020)

Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (J. Signal Process. Syst., 2020)

High-Throughput FFT-SPA Decoder Implementation for Non-Binary LDPC Codes on x86 Multicore Processors. - Bertrand Le Gal; Christophe Jégo (J. Signal Process. Syst., 2020)

Extended RISC-V hardware architecture for future digital communication systems. - Maël Tourres; Cyrille Chavet; Bertrand Le Gal; Jérémie Crenne; Philippe Coussy (5GWF, 2021)

Time sliding window for the detection of CCSK frames. - Camille Monière; Kassem Saied; Bertrand Le Gal; Emmanuel Boutillon (SiPS, 2021)

Flexible design methodology for spike encoding implementation on FPGA. - Clémence Gillet; Adrien F. Vincent; Bertrand Le Gal; Sylvain Saïghi (BioCAS, 2022)

High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices. - Bertrand Le Gal; Vincent Pignoly; Christophe Jégo (DASIP, 2022)

Efficient Software and Hardware Implementations of a QCSP Communication System. - Camille Monière; Bertrand Le Gal; Emmanuel Boutillon (DASIP, 2022)

High-throughput FFT architectures using HLS tools. - Hugues Almorin; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo; Vincent Kissel (ICECS 2022, 2022)

Efficient LoRa-like Transmitter Stacks for SDR Applications. - Léa Volpin; Bertrand Le Gal; Guillaume Ferré (ICECS 2022, 2022)

Methodology to Adapt Neural Network on Constrained Device at Topology level. - Logan Saint-Germain; Bertrand Le Gal; Fabien Baldacci; Jérémie Crenne; Christophe Jégo; Sebastien Loty (SiPS, 2022)

Adéquation Algorithme Architecture - Approches matérielles et logicielles pour les applications de communications numériques. (Algorithm Architecture Matching - Hardware and software approaches for digital communications applications). - Bertrand Le Gal (2023)

Securing a RISC-V architecture: A dynamic approach. - Sébastien Pillement; Maria Mendez Real; J. Pottier; T. Nieddu; Bertrand Le Gal; Sébastien Faucou; Jean-Luc Béchennec; Mikaël Briday; Sylvain Girbal; Jimmy Le Rhun; Olivier Gilles; Daniel Gracia Pérez; et al. (DATE, 2023)

Model Based Design of FMCW Radar Processing Systems on FPGA Platforms. - Hugues Almorin; Bertrand Le Gal; Christophe Jégo; Vincent Kissel (DSD, 2023)

Implementation of an Assignment Algorithm for Object Tracking on a FPGA MPSoC. - Denis Shemonaev; Bertrand Le Gal; Christophe Jégo; Anthony Besseau (DSD, 2023)

Real-Time Low-Earth Orbit Detector Implementation for Chirp-Based Preamble Communication Systems. - Matthieu Magnant; Mohamed Amine Ben Temim; Bertrand Le Gal; Guillaume Ferré; Florian Collard (LATINCOM, 2023)

The Smart Kalman Filter: A Deep Learning-Based Approach for Time-Varying Channel Estimation. - Antoine Siebert; Guillaume Ferré; Bertrand Le Gal; Aurélien Fourny (PIMRC, 2023)

A High-Level Methodology to Evaluate and Optimize Digital Architectures Targeting Spike Encoding. - Clémence Gillet; Adrien F. Vincent; Bertrand Le Gal; Sylvain Saïghi (IEEE Access, 2023)

Real-time energy-efficient software and hardware implementations of a QCSP communication system. - Camille Monière; Bertrand Le Gal; Emmanuel Boutillon (J. Syst. Archit., 2023)

High-performance hard-input LDPC decoding on multi-core devices for optical space links. - Bertrand Le Gal; Christophe Jégo; Vincent Pignoly (J. Syst. Archit., 2023)

Joint Blind Estimation and Equalization Method Based on Deep Learning for Fast Fading Channels. - Antoine Siebert; Guillaume Ferré; Bertrand Le Gal; Aurélien Fourny (NewCAS, 2024)

RISC-V processor enhanced with a dynamic micro-decoder unit. - Juliette Pottier; Thomas Nieddu; Bertrand Le Gal; Sébastien Pillement; Maria Méndez Real (CoRR, 2024)

Scalable High-Throughput and Low-Latency DVB-S2(x) LDPC Decoders on SIMD Devices. - Bertrand Le Gal (IEEE Open J. Commun. Soc., 2024)

Implementation of A Low-Earth Orbit Satellite Chirped Preamble Detector. - Matthieu Magnant; Bertrand Le Gal; Guillaume Ferré; Florian Collard (IEEE Trans. Aerosp. Electron. Syst., 2024)

Differential Delay Mitigation in Multi-Antenna Aircraft Transmissions. - Oussama Ait Sidi Ali; Romain Tajan; Bertrand Le Gal; Alain Thomas (VTC2025-Spring, 2025)

Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors. - Maël Tourres; Cyrille Chavet; Bertrand Le Gal; Philippe Coussy (IEEE Access, 2025)