A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization. - Yoonmyung Lee; Bharan Giridhar; Zhiyoong Foo; Dennis Sylvester; David T. Blaauw (ISSCC, 2011)

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. - David Fick; Ronald G. Dreslinski; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (ISSCC, 2012)

Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating. - Bharan Giridhar; Matthew Fojtik; David Fick; Dennis Sylvester; David T. Blaauw (CICC, 2013)

Scaling towards kilo-core processors with asymmetric high-radix topologies. - Nilmini Abeyratne; Reetuparna Das; Qingkun Li; Korey Sewell; Bharan Giridhar; Ronald G. Dreslinski; David T. Blaauw; Trevor N. Mudge (HPCA, 2013)

A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution. - Suyoung Bang; Allan Wang; Bharan Giridhar; David T. Blaauw; Dennis Sylvester (ISSCC, 2013)

Exploring DRAM organizations for energy-efficient and resilient exascale memories. - Bharan Giridhar; Michael Cieslak; Deepankar Duggal; Ronald G. Dreslinski; Hsing Min Chen; Robert Patti; Betina Hold; Chaitali Chakrabarti; Trevor N. Mudge; David T. Blaauw (SC, 2013)

Centip3De: a many-core prototype exploring 3D integration and near-threshold computing. - Ronald G. Dreslinski; David Fick; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (Commun. ACM, 2013)

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS. - David Fick; Ronald G. Dreslinski; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (IEEE J. Solid State Circuits, 2013)

A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes. - Yoonmyung Lee; Bharan Giridhar; Zhiyoong Foo; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2013)

Centip3De: A 64-Core, 3D Stacked Near-Threshold System. - Ronald G. Dreslinski; David Fick; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (IEEE Micro, 2013)

Integrated 3D-stacked server designs for increasing physical density of key-value stores. - Anthony Gutierrez; Michael Cieslak; Bharan Giridhar; Ronald G. Dreslinski; Luis Ceze; Trevor N. Mudge (ASPLOS, 2014)

13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS. - Bharan Giridhar; Nathaniel Ross Pinckney; Dennis Sylvester; David T. Blaauw (ISSCC, 2014)