Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. - Andreas Dandalis; Viktor K. Prasanna; Bharani Thiruvengadam (FPL, 2001)

A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS. - Harish Krishnamurthy; Vaibhav A. Vaidya; Pavan Kumar 001; George E. Matthew; Sheldon Weng; Bharani Thiruvengadam; Wayne Proefrock; Krishnan Ravichandran; Vivek De (VLSIC, 2014)

A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS. - Pavan Kumar 001; Vaibhav A. Vaidya; Harish Krishnamurthy; Stephen T. Kim; George E. Matthew; Sheldon Weng; Bharani Thiruvengadam; Wayne Proefrock; Krishnan Ravichandran; Vivek De (CICC, 2015)