Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. - Bharat Krishna; C. Y. Roger Chen; Naresh Sehgal (VLSI Design, 1998)

A novel technique for sea of gates global routing. - Bharat Krishna; C. Y. Roger Chen; Naresh Sehgal (ACM Great Lakes Symposium on VLSI, 2000)

A novel ultra-fast heuristic for VLSI CAD steiner trees. - Bharat Krishna; C. Y. Roger Chen; Naresh Sehgal (ACM Great Lakes Symposium on VLSI, 2003)