Switch-level simulation of total dose effects on CMOS VLSI circuits. - Bharat L. Bhuva; John J. Paulos; Ronald S. Gyurcsik; Sherra E. Kerns (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Multi-level qualitative reasoning applied to CMOS digital circuits. - Neeraj Kaul; Gautam Biswas; Bharat L. Bhuva (Artif. Intell. Eng., 1992)

Statistical degradation analysis of digital CMOS IC's. - Venkata S. Rangavajjhala; Bharat L. Bhuva; Sherra E. Kerns (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Design Technique for Mitigation of Soft Errors in Differential Switched-Capacitor Circuits. - Patrick R. Fleming; Brian D. Olson; W. Timothy Holman; Bharat L. Bhuva; Lloyd W. Massengill (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. - David Rennie; David Li 002; Manoj Sachdev; Bharat L. Bhuva; Srikanth Jagannathan; Shi-Jie Wen; Rick Wong (CICC, 2011)

Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits. - Daniel B. Limbrick; Suge Yue; William H. Robinson; Bharat L. Bhuva (DFT, 2011)

Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter. - Yi Ren; L. Fan; Li Chen 001; Shi-Jie Wen; Richard Wong; N. W. van Vonno; Arthur F. Witulski; Bharat L. Bhuva (J. Electron. Test., 2012)

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. - David Rennie; David Li 002; Manoj Sachdev; Bharat L. Bhuva; Srikanth Jagannathan; Shi-Jie Wen; Richard Wong (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients. - Zhichao Zhang; Yi Ren; Li Chen 001; Nelson J. Gaspard; Arthur F. Witulski; W. Timothy Holman; Bharat L. Bhuva; Shi-Jie Wen; Ramaswami Sammynaiken (J. Electron. Test., 2013)

An efficient technique to select logic nodes for single event transient pulse-width reduction. - Nihaar N. Mahatme; Indranil Chatterjee; Akash Patki; Daniel B. Limbrick; Bharat L. Bhuva; Ronald D. Schrimpf; William H. Robinson (Microelectron. Reliab., 2013)

Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser. - Yi Ren; Anlin He; Shuting Shi; Gang Guo; Li Chen 001; Shi-Jie Wen; Richard Wong; N. W. van Vonno; Bharat L. Bhuva (J. Electron. Test., 2014)

Terrestrial SER characterization for nanoscale technologies: A comparative study. - Nihaar N. Mahatme; Bharat L. Bhuva; Nelson J. Gaspard; T. Assis; Y. Xu; P. Marcoux; M. Vilchis; Balaji Narasimham; A. Shih; Shi-Jie Wen; Rick Wong; N. Tam; et al. (IRPS, 2015)

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. - Balaji Narasimham; Jung K. Wang; Narayana Vedula; Saket Gupta; Brandon Bartz; Carl Monzel; Indranil Chatterjee; Bharat L. Bhuva; Ronald D. Schrimpf; Robert A. Reed (IRPS, 2015)

Multi-cell soft errors at the 16-nm FinFET technology node. - N. Tam; Bharat L. Bhuva; Lloyd W. Massengill; Dennis R. Ball; Michael W. McCurdy; Michael L. Alles; Indranil Chatterjee (IRPS, 2015)

Single-event performance of differential flip-flop designs and hardening implication. - Rongmei Chen; Enxia Zhang; Bharat L. Bhuva (IOLTS, 2016)

Impact of supply voltage and particle LET on the soft error rate of logic circuits. - Hui Jiang; H. Zhang; R. C. Harrington; J. A. Maharrey; J. S. Kauppila; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)

Designing soft-error-aware circuits with power and speed optimization. - H. Jiang; H. Zhang; Balaji Narasimham; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)

Single-event effects on optical transceiver. - Kurt J. Lezon; Shi-Jie Wen; Y.-F. Dan; Richard Wong; Bharat L. Bhuva (IRPS, 2018)

Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. - H. Zhang; H. Jiang; M. R. Eaker; Kurt J. Lezon; Balaji Narasimham; Nihaar N. Mahatme; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)

A TCAD evaluation of a single Bulk-BICS with integrative memory cell. - Alexandre Simionovski; Gilson I. Wirth; Ronald D. Schrimpf; Bharat L. Bhuva (Microelectron. J., 2018)

Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies. - Jingchen Cao; Lyuan Xu; Bharat L. Bhuva; Shi-Jie Wen; Richard Wong; Balaji Narasimham; Lloyd W. Massengill (IRPS, 2019)

Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. - Balaji Narasimham; K. Chandrasekharan; J. K. Wang; Bharat L. Bhuva (IRPS, 2019)

Neutron Beam Attenuation Through Semiconductor Devices During SEU Testing. - S. A. Wender; J. M. O'Donnell; Lukas Zavorka; Bharat L. Bhuva (IRPS, 2019)

Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology. - Lyuan Xu; Jingchen Cao; Bharat L. Bhuva; Indranil Chatterjee; Shi-Jie Wen; Richard Wong; Lloyd W. Massengill (IRPS, 2019)

Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology. - Jingchen Cao; Lyuan Xu; Shi-Jie Wen; Rita Fung; Balaji Narasimham; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2020)

Thermal Neutron Induced Soft Errors in 7-nm Bulk FinFET Node. - Lyuan Xu; Jingchen Cao; John Brockman; Carlo Cazzaniga; Christopher Frost 002; Shi-Jie Wen; Rita Fung; Bharat L. Bhuva (IRPS, 2020)

High-Current State triggered by Operating-Frequency Change. - Lyuan Xu; Jingchen Cao; Shi-Jie Wen; Rita Fung; Jamie Markevitch; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2020)

Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology. - Alexandra Feeley; Yoni Xiong; Bharat L. Bhuva; Balaji Narasimham; Shi-Ji Wen; Rita Fung (IRPS, 2021)

Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET. - Balaji Narasimham; Vikas Chaudhary; Mike Smith; Liming Tsau; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2021)

Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node. - Yoni Xiong; Alexandra Feeley; Lloyd W. Massengill; Bharat L. Bhuva; Shi-Jie Wen; Rita Fung (IRPS, 2021)

Single-Event Latchup Vulnerability at the 7-nm FinFET Node. - Nicholas J. Pieper; Yoni Xiong; Alexandra Feeley; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2022)

Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment. - Yoni Xiong; Alexandra Feeley; Nicholas J. Pieper; Dennis R. Ball; Balaji Narasimham; John Brockman; N. A. Dodds; S. A. Wender; Shi-Jie Wen; Rita Fung; Bharat L. Bhuva (IRPS, 2022)

Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node. - Nicholas J. Pieper; Yoni Xiong; Dennis R. Ball; J. Pasternak; Bharat L. Bhuva (IRPS, 2023)

Soft Error Rate Predictions for Terrestrial Neutrons at the 3-nm Bulk FinFET Technology. - Yoni Xiong; Yueh Chiang; Nicholas J. Pieper; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2023)

Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages. - Jenna B. Kronenberg; Yoni Xiong; Nicholas J. Pieper; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2024)

Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET. - Balaji Narasimham; A-R. Montoya; C. Paone; T. Riehle; Mike Smith; Liming Tsau; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2024)

Total-Ionizing Dose Damage from X-Ray PCB Inspection Systems. - Nicholas J. Pieper; M. Chun; Yoni Xiong; H. M. Dattilo; Jenna B. Kronenberg; Sanghyeon Baeg; Shi-Jie Wen; Rita Fung; D. Chan; C. Escobar; Bharat L. Bhuva (IRPS, 2024)

Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node. - Yoni Xiong; Nicholas J. Pieper; Jenna B. Kronenberg; Dennis R. Ball; Megan Casey; Bharat L. Bhuva (IRPS, 2024)

Power-Aware Mitigation of Logic Soft Error Rates at the 3-nm Bulk FinFET Node. - Jenna B. Kronenberg; Y. Xiong; Nicholas J. Pieper; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2025)

Power and SER Performance of Flip-Flop Cells with Low-Leakage Options. - Nicholas J. Pieper; Y. Xiong; Jenna B. Kronenberg; R. Fung; Dennis R. Ball; Bharat L. Bhuva (IRPS, 2025)