Bharath Narasimha Swamy

Orcid: 0000-0002-3875-5236

According to our database1, Bharath Narasimha Swamy authored at least 8 papers between 2014 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2018
DITVA: Dynamic Inter-Thread Vectorization Architecture.
J. Parallel Distributed Comput., 2018

2016
Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

2015
Exploiting heterogeneous manycores on sequential code. (Utilisation de manycores hétérogènes sur du code séquentiel).
PhD thesis, 2015

Intercepting Functions for Memoization: A Case Study Using Transcendental Functions.
ACM Trans. Archit. Code Optim., 2015

Branch prediction and the performance of interpreters: don't trust folklore.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

An empirical high level performance model for future many-cores.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014


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