21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (ISSCC, 2009)

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (IEEE J. Solid State Circuits, 2010)

11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications. - Namik Kocaman; Adesh Garg; Bharath Raghavan; Delong Cui; Anand Vasani; Keith Tang; Deyi Pi; Haitao Tong; Siavash Fallahi; Wei Zhang; Ullas Singh; Jun Cao 001; et al. (ISSCC, 2011)

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications. - Namik Kocaman; Adesh Garg; Bharath Raghavan; Delong Cui; Anand Vasani; Keith Tang; Deyi Pi; Haitao Tong; Siavash Fallahi; Wei Zhang; Ullas Singh; Jun Cao 001; et al. (IEEE J. Solid State Circuits, 2011)

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Tamer A. Ali 001; Nick Huang; Wei Zhang; et al. (ISSCC, 2012)

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Wei Zhang; Tamer A. Ali 001; Nick Huang; et al. (IEEE J. Solid State Circuits, 2012)

A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. - Bharath Raghavan; Delong Cui; Ullas Singh; Hassan Maarefi; Dave Pi; Anand Vasani; Zhi Chao Huang; Afshin Momtaz; Jun Cao 001 (ISSCC, 2013)

A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS. - Bharath Raghavan; Delong Cui; Ullas Singh; Hassan Maarefi; Deyi Pi; Anand Vasani; Zhi Chao Huang; Burak Çatli; Afshin Momtaz; Jun Cao 001 (IEEE J. Solid State Circuits, 2013)

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS. - Ullas Singh; Adesh Garg; Bharath Raghavan; Nick Huang; Heng Zhang; Zhi Huang; Afshin Momtaz; Jun Cao 001 (ISSCC, 2014)

A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS. - Ullas Singh; Adesh Garg; Bharath Raghavan; Nick Huang; Heng Zhang; Zhi Chao Huang; Afshin Momtaz; Jun Cao 001 (IEEE J. Solid State Circuits, 2014)

A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS. - Bharath Raghavan; Aida Varzaghani; Lakshmi P. Rao; Henry Park; Xiaochen Yang; Zhi Huang; Yu Chen; Rama Kattamuri; Chunhui Wu; Bo Zhang 029; Jun Cao 001; Afshin Momtaz; et al. (VLSI Circuits, 2016)

An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology. - Namik Kocaman; Ullas Singh; Bharath Raghavan; Arvindh Iyer; Kumar Thasari; Saurabh Surana; Jun Won Jung; Jaehun Jeong; Heng Zhang; Anand Vasani; Yonghyun Shim; Zhi Huang; et al. (ISSCC, 2022)

MiMiCPy: An Efficient Toolkit for MiMiC-Based QM/MM Simulations. - Bharath Raghavan; Florian K. Schackert; Andrea Levy; Sophia K. Johnson; Emiliano Ippoliti; Davide Mandelli; Jógvan Magnus Haugaard Olsen; Ursula Rothlisberger; Paolo Carloni (J. Chem. Inf. Model., 2023)

Drug Design in the Exascale Era: A Perspective from Massively Parallel QM/MM Simulations. - Bharath Raghavan; Mirko Paulikat; Katya Ahmad; Lara Callea; Andrea Rizzi; Emiliano Ippoliti; Davide Mandelli; Laura Bonati; Marco de Vivo; Paolo Carloni (J. Chem. Inf. Model., 2023)