Effective false positive filtering for evolving software. - Bharti Chimdyalwar; Shrawan Kumar 001 (ISEC, 2011)

Survey of array out of bound access checkers for C code. - Bharti Chimdyalwar (ISEC, 2012)

Precise range analysis on large industry code. - Shrawan Kumar 001; Bharti Chimdyalwar; Ulka Shrotri (ESEC/SIGSOFT FSE, 2013)

Over-approximating loops to prove properties using bounded model checking. - Priyanka Darke; Bharti Chimdyalwar; R. Venkatesh 001; Ulka Shrotri; Ravindra Metta (DATE, 2015)

Eliminating Static Analysis False Positives Using Loop Abstraction and Bounded Model Checking. - Bharti Chimdyalwar; Priyanka Darke; Anooj Chavda; Sagar Vaghani; Avriti Chauhan (FM, 2015)

Efficient Safety Proofs for Industry-Scale Code Using Abstractions and Bounded Model Checking. - Priyanka Darke; Bharti Chimdyalwar; Avriti Chauhan; R. Venkatesh 001 (ICST, 2017)

VeriAbs: Verification by Abstraction (Competition Contribution). - Bharti Chimdyalwar; Priyanka Darke; Avriti Chauhan; Punit Shah; Shrawan Kumar 001; R. Venkatesh 001 (TACAS (2), 2017)

Statically relating program properties for efficient verification (short WIP paper). - Bharti Chimdyalwar; Priyanka Darke (LCTES, 2018)

VeriAbs: Verification by Abstraction and Test Generation - (Competition Contribution). - Priyanka Darke; Sumanth Prabhu 001; Bharti Chimdyalwar; Avriti Chauhan; Shrawan Kumar 001; Animesh Basak Chowdhury; R. Venkatesh 001; Advaita Datar; Raveendra Kumar Medicherla (TACAS (2), 2018)

VeriAbs : Verification by Abstraction and Test Generation. - Mohammad Afzal; Asia A; Avriti Chauhan; Bharti Chimdyalwar; Priyanka Darke; Advaita Datar; Shrawan Kumar 001; R. Venkatesh 001 (ASE, 2019)

VeriAbs : Verification by Abstraction and Test Generation (Competition Contribution). - Mohammad Afzal; Supratik Chakraborty; Avriti Chauhan; Bharti Chimdyalwar; Priyanka Darke; Ashutosh Gupta 001; Shrawan Kumar 001; Charles Babu M; Divyesh Unadkat; R. Venkatesh 001 (TACAS (2), 2020)

Fast Change-Based Alarm Reporting for Evolving Software Systems. - Anushri Jana; Ankita Khadsare; Bharti Chimdyalwar; Shrawan Kumar 001; Vaidehi Ghime; R. Venkatesh 001 (ISSRE, 2021)

Selective path-sensitive interval analysis (WIP paper). - Bharti Chimdyalwar; Shrawan Kumar 001 (LCTES, 2021)

IR Mapping: Intermediate Representation (IR) based Mapping to facilitate Incremental Static Analysis. - Vaidehi Ghime; Ankita Khadsare; Anushri Jana; Bharti Chimdyalwar (ISEC, 2022)

Fast Analysis of Evolving Software Systems. - Anushri Jana; Bharti Chimdyalwar; Shrawan Kumar 001; R. Venkatesh 001 (ISSRE Workshops, 2022)

Identifying Relevant Changes for Incremental Verification of Evolving Software Systems. - Bharti Chimdyalwar; Anushri Jana; Shrawan Kumar 001; Ankita Khadsare; Vaidehi Ghime (SANER, 2022)

OLA: Property Directed Outer Loop Abstraction for Efficient Verification of Reactive Systems. - Priyanka Darke; Bharti Chimdyalwar (ICSME, 2023)

VeriAbsL: Scalable Verification by Abstraction and Strategy Prediction (Competition Contribution). - Priyanka Darke; Bharti Chimdyalwar; Sakshi Agrawal; Shrawan Kumar 001; R. Venkatesh 001; Supratik Chakraborty (TACAS (2), 2023)

The VeriAbs Tool Suite for Code Verification. - Priyanka Darke; Bharti Chimdyalwar; R. Venkatesh 001; Supratik Chakraborty (ATVA, 2024)

Learning Strategies Using Boolean Program Metrics to Verify Industrial Code. - Priyanka Darke; Bharti Chimdyalwar; Manoj Alladawar; Sahil Sulakhe; R. Venkatesh 001; Supratik Chakraborty (ICSME, 2024)

Fast and Precise Interval Analysis on Industry code. - Bharti Chimdyalwar (ISSRE (Workshops), 2024)