A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. - Bhaskar Chatterjee; Manoj Sachdev; Ali Keshavarzi (ITC, 2002)

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. - Bhaskar Chatterjee; Manoj Sachdev; Steven Hsu; Ram Krishnamurthy 001; Shekhar Borkar (ISLPED, 2003)

Modeling and designing energy-delay optimized wide domino circuits. - Christine Kwong; Bhaskar Chatterjee; Manoj Sachdev (ISCAS (2), 2004)

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. - Bhaskar Chatterjee; Manoj Sachdev; Ram Krishnamurthy 001 (ISLPED, 2004)

Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. - Bhaskar Chatterjee; Manoj Sachdev; Ram Krishnamurthy 001 (ISQED, 2004)

A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. - Bhaskar Chatterjee; Manoj Sachdev; Ali Keshavarzi (ITC, 2004)

DFT for Delay Fault Testing of High-Performance Digital Circuits. - Bhaskar Chatterjee; Manoj Sachdev; Ali Keshavarzi (IEEE Des. Test Comput., 2004)

Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. - Bhaskar Chatterjee; Manoj Sachdev; Ram Krishnamurthy 001 (Microelectron. J., 2005)

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. - Bhaskar Chatterjee; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2005)