Implementation of a Novel Phoneme Recognition System Using TMS320C6713 DSP. - J. Manikandan; B. Venkataramani; M. Bhaskar 001; K. Ashish; R. Raghul; V. Mathangi (VLSI Design, 2010)

Design of a novel differential on-chip wave-pipelined serial interconnect with surfing. - M. Bhaskar 001; A. Jaswanth; B. Venkataramani (Microprocess. Microsystems, 2013)

Differential Voltage Mode On-Chip Serial Transceiver for Global Interconnects. - M. Bhaskar 001; B. Venkataramani (J. Low Power Electron., 2014)

FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT. - Thilagavathy R; Susmitha Settivari; Venkataramani B; Bhaskar Manickam (VDAT, 2017)

Gyrator-C Based Bandpass Filter with Improved Dynamic Range for Fully Integrated RF Front-End. - Lakshmi Nediyara Suresh; Bhaskar Manickam (ISVLSI, 2018)

Improved Heart Rate Estimation from Photoplethysmography During Physical Exercise Using Combination of NLMS and RLS Adaptive Filters. - Arunkumar KR; Ram Srivathsa; Bhaskar Manickam (TENCON, 2018)

A low power wideband low-noise amplifier with input series peaking and $g_{m}$ enhancement for 0.5 - 3.5 GHz applications. - J. Pradeep; S. Chrisben Gladson; M. Bhaskar 001 (TENCON, 2019)

A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifier. - Archana Sunitha; Bhaskar Manickam (VDAT, 2019)

Heart rate estimation from photoplethysmography signal for wearable health monitoring devices. - Arunkumar KR; Bhaskar Manickam (Biomed. Signal Process. Control., 2019)

Co-design of on-chip loop antenna and differential class-E power amplifier at 2.4 GHz for biotelemetry applications. - Archana Sunitha; Bhaskar Manickam (Microelectron. J., 2019)

Design and Implementation of 1024 Point Pipelined Radix 4 FFT Processor on FPGA for Biomedical Signal Processing Applications. - Aditya Sankaran; M. Srikanth Reddy; K. R. Arunkumar; M. Bhaskar 001 (iSES, 2020)

Heart rate estimation from wrist-type photoplethysmography signals during physical exercise. - Arunkumar KR; M. Bhaskar 001 (Biomed. Signal Process. Control., 2020)

A 3-stage RF down-converter exploiting body-effect for IEEE 802.15.4 applications. - S. Chrisben Gladson; M. Bhaskar 001 (Comput. Electr. Eng., 2020)

Multiple cascode flipped active inductor-based tunable bandpass filter for fully integrated RF front-end. - Lakshmi Nediyara Suresh; Bhaskar Manickam (IET Circuits Devices Syst., 2020)

An inductorless 1.8 ​mW 2.9 ​dB NF differential LNA integrated to on-chip loop antenna with secondary loop for biomedical applications. - Archana Sunitha; Bhaskar Manickam (Microelectron. J., 2020)

CASINOR: Combination of adaptive filters using single noise reference signal for heart rate estimation from PPG signals. - K. R. Arunkumar; M. Bhaskar 001 (Signal Image Video Process., 2020)

Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator. - Krishna Sai Tarun Ramapragada; Ajith Kumar Reddy Netla; Pavan Kalyan Chattada; Bhaskar Manickam (iSES, 2021)

A 4-6 GHz Single-Ended to Differential-Ended Low-Noise Amplifier for IEEE 802.11ax Wireless Applications with Inherent Complementary Distortion Cancellation. - S. Chrisben Gladson; P. Siva Prasad; V. Thenmozhi; M. Bhaskar 001 (J. Circuits Syst. Comput., 2021)

Design of Active Inductor-Based VCO with Wide Tuning Range for RF Front End. - Lakshmi Nediyara Suresh; Bhaskar Manickam (Circuits Syst. Signal Process., 2022)

A 60-GHz low-noise amplifier with +7.258-dBm third-order input intercept point using current reuse feedforward distortion cancellation for 5G emerging communication. - Thenmozhi Veerasamy; Bhaskar Manickam (Int. J. Circuit Theory Appl., 2022)

Design and application of CMOS active inductor in bandpass filter and VCO for reconfigurable RF front-end. - Lakshmi Nediyara Suresh; Bhaskar Manickam (Integr., 2022)

An Integrated 2.4 GHz Inductorless Power Amplifier and On-Chip Two Turn Folded Loop Antenna for biotelemetry applications. - Archana Sunitha; M. Bhaskar 001 (ICCCNT, 2023)

FPGA Implementation of Modified Lightweight 128-Bit AES Algorithm for IoT Applications. - Jeyvarshni Vimalkumar; Harshitha Ramesh Babu; M. Bhaskar 001 (iSES, 2023)

Design and FPGA Implementation of Pre-computation Based Radix-4 Hyperbolic CORDIC for Direct Digital Synthesis. - Shubhanjay S. Pujari; M. Bhaskar 001 (J. Signal Process. Syst., 2023)

A 3.5GHz Reconfigurable 2-Stage Cascode CMOS LNA with HPF Noise Matching & Body Bias for 5G NR n78 Band Applications. - Hridhay Natanasubramanian; Chandana S; M. Bhaskar 001 (ICDCS, 2024)