Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver. - Shankarram Athreya; Hiva Hedayati; Shayan Kazemkhani; Yanfei Chen; Saurabh Vats; Michael D. Scott 002; Bart Zeydel; Peter Keller; Jian Wang; Bhaskarareddy Avula; Boris Murmann; Echere Iroaga (ESSCIRC, 2018)