Generic and programmable Timing Generator for CCD detectors. - Parth Shah; Bhavesh Soni; Mohammad Waris; Rajiv Kumaran; Sanjeev Mehta; Arup Roy Chowdhury (ICACCI, 2014)

Power Budget Improvement Using Floorplan Methodologies In Lower(28nm) Technology Node. - Vidhi Gandhi; Yashvi Patel; Bhavesh Soni; Gaurav Joshi (iSES, 2023)

Performance Enhancement of "ARP Block" using 28nm Technology node. - Vishal Mahida; Bhavesh Soni; Nilesh Ranpura (iSES, 2023)

IR Drop Mitigation Methodologies in 90nm Technology Node for Networking Chip. - Dipesh Panchal; Chandni Patel; Bhavesh Soni (iSES, 2023)

Design & Implementation of Novel Asynchronous FIFO. - Vijay Patel; Vimal Mer; Jignesh J. Patoliya; Bhavesh Soni (iSES, 2023)

Practical Analysis of Various Approaches for Targeting Delay Faults at Functional Frequency in Automatic Test Pattern Generation (ATPG). - Bhavesh Soni; Kishor Purohit; Dhaval Fichadia (iSES, 2023)

Performance Evaluation of Parallel Processing Adder Against Basic Adders on FPGAs. - Dhaval Fichadia; Kishor Purohit; Bhavesh Soni (COMS2, 2024)

Enhancing ASIC Design Efficiency: A Focus on RTL Verification with Spyglass. - Dhaval Fichadia; Nikeeta Shah; Bhavesh Soni (COMS2, 2024)

Design and Optimization in SPI Master at the RTL Level. - Rajat R. Sahu; Mitur Patel; Bhavesh Soni; Jignesh J. Patoliya (COMS2, 2024)