High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. - Avadhoot Khairnar; Bhavuk Chauhan; Geetanjali Sharma; Amit M. Joshi 001 (J. Circuits Syst. Comput., 2022)

Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. - Avadhoot Khairnar; Bhavuk Chauhan; Geetanjali Sharma; Amit M. Joshi 001 (J. Circuits Syst. Comput., 2022)