Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack. - Bhuvana B. P.; V. S. Kanchana Bhaaskaran (VLSID, 2018)

Design and Analysis of FinFET Based CSCPAL Low Power Adder. - Jayashree K. G; Lois Priscilla S; Bhuvana B. P.; V. S. Kanchana Bhaaskaran (iSES, 2019)

Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications. - Bhuvana B. P.; V. S. Kanchana Bhaaskaran (Microelectron. J., 2019)

Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS). - E. Ramkumar; D. Gracin; P. Rajkamal; Bhuvana B. P.; V. S. Kanchana Bhaaskaran (iSES, 2020)

Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures. - Bhuvana B. P.; V. S. Kanchana Bhaaskaran (J. Circuits Syst. Comput., 2020)