Bi Wu

Orcid: 0000-0001-9972-0478

Affiliations:

Nanjing University of Aeronautics and Astronautics, Nanjing, China

According to our database¹, Bi Wu authored at least 46 papers between 2015 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2025

LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025

Learning-Based Realtime Synthetic Aperture Radar Imaging for Embedded System on Satellite.

[BibT_eX]

[DOI]

Tianyang Yu

Bi Wu

Weiqiang Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, December, 2024

A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024

Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, February, 2024

Most Significant One-Driven Shifting Dynamic Efficient Multipliers for Large Language Models.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024

2023

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

A Survey of MRAM-Centric Computing: From Near Memory to In Memory.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

Low-cost stochastic number generator based on MRAM for stochastic computing.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

A High-Speed CNN Hardware Accelerator with Regular Pruning.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

A NAND-SPIN-Based Magnetic ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

2019

An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.

[BibT_eX]

[DOI]

Jacques-Olivier Klein

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2016

PDS: pseudo-differential sensing scheme for STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Bi Wu

Timeline

Legend:

Links

Online presence:

On csauthors.net:

Bibliography

Loading...