An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. - Bi Wu 002; Yuanqing Cheng; Ying Wang 001; Aida Todri-Sanial; Guangyu Sun 003; Lionel Torres; Weisheng Zhao (NANOARCH, 2015)

PDS: pseudo-differential sensing scheme for STT-MRAM. - Wang Kang 001; Tingting Pang; Bi Wu 002; Weifeng Lv; Youguang Zhang; Guangyu Sun 003; Weisheng Zhao (DAC, 2016)

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. - Bi Wu 002; Yuanqing Cheng; Jianlei Yang 001; Aida Todri-Sanial; Weisheng Zhao (IEEE Trans. Reliab., 2016)

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. - Bi Wu 002; Yuanqing Cheng; Pengcheng Dai; Jianlei Yang 001; Youguang Zhang; Dijun Liu; Ying Wang 001; Weisheng Zhao (ICCAD, 2017)

Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. - Bi Wu 002; Xiaolong Zhang; Yuanqing Cheng; Zhaohao Wang; Dijun Liu; Youguang Zhang; Weisheng Zhao (ISVLSI, 2018)

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. - Linuo Xue; Bi Wu 002; Beibei Zhang; Yuanqing Cheng; Peiyuan Wang; Chando Park; Jimmy J. Kan; Seung-Hyuk Kang; Yuan Xie 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Ultra-Dense Ring-Shaped Racetrack Memory Cache Design. - Guanda Wang; Yue Zhang 010; Beibei Zhang; Bi Wu 002; Jiang Nan; Xueying Zhang; Zhizhong Zhang 004; Jacques-Olivier Klein; Dafine Ravelosona; Zhaohao Wang; Youguang Zhang; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. - Bi Wu 002; Beibei Zhang; Yuanqing Cheng; Ying Wang 001; Dijun Liu; Weisheng Zhao (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion. - Wang Kang 001; Bi Wu 002; Xing Chen; Daoqian Zhu; Zhaohao Wang; Xichao Zhang; Yan Zhou; Youguang Zhang; Weisheng Zhao (ACM J. Emerg. Technol. Comput. Syst., 2020)

Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization. - Jiacheng Ni; Keren Liu; Bi Wu 002; Weisheng Zhao; Yuanqing Cheng; Xiaolong Zhang; Ying Wang 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. - Bi Wu 002; Pengcheng Dai; Yuanqing Cheng; Ying Wang 001; Jianlei Yang 001; Zhaohao Wang; Dijun Liu; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories. - Bi Wu 002; Chao Wang 094; Zhaohao Wang; Ying Wang 001; Deming Zhang; Dijun Liu; Youguang Zhang; Xiaobo Sharon Hu (IEEE Trans. Circuits Syst., 2020)

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. - Bi Wu 002; Weisheng Zhao; Xiaobo Sharon Hu; Pengcheng Dai; Zhaohao Wang; Chao Wang 094; Ying Wang 001; Jianlei Yang 001; Yuanqing Cheng; Dijun Liu; Youguang Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity. - Guocai Nan; Zhengkuan Wang; Chenghua Wang; Bi Wu 002; Zhican Wang; Weiqiang Liu 001; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A NAND-SPIN-Based Magnetic ADC. - Bi Wu 002; Zhaohao Wang; Yuxuan Li; Ying Wang 001; Dijun Liu; Weisheng Zhao; Xiaobo Sharon Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications. - Jipeng Ge; Chenggang Yan 002; Xuan Zhao; Ke Chen 018; Bi Wu 002; Weiqiang Liu 001 (APCCAS, 2022)

An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits. - Ziying Cui; Ke Chen 018; Bi Wu 002; Chenggang Yan 002; Weiqiang Liu 001 (ACM Great Lakes Symposium on VLSI, 2022)

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy. - Tianyang Yu; Bi Wu 002; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (ACM Great Lakes Symposium on VLSI, 2022)

Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration. - Tianyang Yu; Bi Wu 002; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (ICCD, 2022)

A High-Speed CNN Hardware Accelerator with Regular Pruning. - Yuan Song; Bi Wu 002; Tian Yuan; Weiqiang Liu 001 (ISQED, 2022)

Low-cost stochastic number generator based on MRAM for stochastic computing. - You Wang 002; Bi Wu 002; Hao Cai 001; Weiqiang Liu 001 (NANOARCH, 2022)

High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features. - Kai Liu; Bi Wu 002; Haonan Zhu; Weiqiang Liu 001 (NANOARCH, 2022)

HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation. - Hanghang Wang; Ke Chen 018; Bi Wu 002; Chenghua Wang; Weiqiang Liu 001; Fabrizio Lombardi (NANOARCH, 2022)

Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme. - Didi Zhang; Bi Wu 002; Haonan Zhu; Weiqiang Liu 001 (NANOARCH, 2022)

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms. - Shanshan Liu 001; Bi Wu 002; Ke Chen 018; Weiqiang Liu 001; Máire O'Neill; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy. - Bi Wu 002; Zhengkuan Wang; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications. - Haonan Wang; Ke Chen 018; Chenggang Yan 002; Bi Wu 002; Weiqiang Liu 001 (MWSCAS, 2023)

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing. - Wenzhuo Xie; Chenggang Yan 002; Hanghang Wang; Ke Chen 018; Bi Wu 002; Chenghua Wang; Weiqiang Liu 001 (MWSCAS, 2023)

VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning. - Shuo Ran; Bi Wu 002; Ke Chen 018; Weiqiang Liu 001 (NANOARCH, 2023)

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM. - Bi Wu 002; Haonan Zhu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Survey of MRAM-Centric Computing: From Near Memory to In Memory. - Yueting Li; Tianshuo Bai; Xinyi Xu; Yundong Zhang; Bi Wu 002; Hao Cai 001; Biao Pan; Weisheng Zhao (IEEE Trans. Emerg. Top. Comput., 2023)

An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs. - Bi Wu 002; Haonan Zhu; Dayane Reis; Zhaohao Wang; Ying Wang 001; Ke Chen 018; Weiqiang Liu 001; Fabrizio Lombardi; Xiaobo Sharon Hu (IEEE Trans. Emerg. Top. Comput., 2023)

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing. - Chenggang Yan 002; Yuxuan Cui; Ke Chen 018; Bi Wu 002; Weiqiang Liu 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration. - Ziying Cui; Ke Chen 018; Bi Wu 002; Chenggang Yan 002; Yu Gong 002; Weiqiang Liu 001 (ARITH, 2024)

A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration. - Xidi Ma; Weichen Zhang; Xueyan Wang; Tianyang Yu; Bi Wu 002; Gang Qu 001; Weisheng Zhao (DAC, 2024)

Most Significant One-Driven Shifting Dynamic Efficient Multipliers for Large Language Models. - Bin Gong; Ke Chen 018; Pengfei Huang; Bi Wu 002; Weiqiang Liu 001 (ISCAS, 2024)

Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications. - Tianyang Yu; Bi Wu 002; Ke Chen 018; Gong Zhang 002; Weiqiang Liu 001 (IEEE Trans. Computers, 2024)

Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme. - Bi Wu 002; Tianyang Yu; Ke Chen 018; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization. - Tianyang Yu; Bi Wu 002; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM. - Haonan Zhu; Bi Wu 002; Tianyang Yu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory. - Tianyang Yu; Bi Wu 002; Ke Chen 018; Gong Zhang 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate Computing. - Ziying Cui; Ke Chen 018; Bi Wu 002; Yu Gong 002; Chenggang Yan 002; Weiqiang Liu 001 (DAC, 2025)

MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach. - Xuehui Liu; Xueyan Wang; Tianyang Yu; Chen Cheng; Shuo Ran; Bi Wu 002; Xiaotao Jia; Weiqiang Liu 001; Gang Qu 001; Weisheng Zhao (DAC, 2025)

High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme. - Kai Tian; Bi Wu 002; Ke Chen 018; Weiqiang Liu 001 (ISCAS, 2025)

Learning-Based Realtime Synthetic Aperture Radar Imaging for Embedded System on Satellite. - Tianyang Yu; Bi Wu 002; Weiqiang Liu 001 (ISCAS, 2025)

LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator. - Tianyang Yu; Bi Wu 002; Ke Chen 018; Gong Zhang 002; Weiqiang Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)