PHAST Library - Enabling Single-Source and High Performance Code for GPUs and Multi-cores. - Biagio Peccerillo; Sandro Bartolini (HPCS, 2017)

Parallel Programming in Cyber-Physical Systems. - Sandro Bartolini; Biagio Peccerillo (Cyber-Physical Systems Security, 2018)

Using Wearable Haptics for Thermal Discrimination in Virtual Reality Scenarios. - Guido Gioioso; Maria Pozzi; Mirko Aurilio; Biagio Peccerillo; Giovanni Spagnoletti; Domenico Prattichizzo (AsiaHaptics, 2018)

Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous Architectures. - Biagio Peccerillo; Sandro Bartolini (PMAM@PPoPP, 2019)

Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs. - Biagio Peccerillo; Sandro Bartolini; Çetin Kaya Koç (J. Cryptogr. Eng., 2019)

PHAST - A Portable High-Level Modern C++ Programming Library for GPUs and Multi-Cores. - Biagio Peccerillo; Sandro Bartolini (IEEE Trans. Parallel Distributed Syst., 2019)

Using PHAST to port Caffe library: First experiences and lessons learned. - Eduardo José Gómez-Hernández; Pablo Antonio Martínez; Biagio Peccerillo; Sandro Bartolini; José Manuel García Carrasco; Gregorio Bernabé (CoRR, 2020)

A General Framework for Accelerator Management Based on ISA Extension. - Elham Cheshmikhani; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2022)

Applying Intel's oneAPI to a machine learning case study. - Pablo Antonio Martínez; Biagio Peccerillo; Sandro Bartolini; José M. García 001; Gregorio Bernabé (Concurr. Comput. Pract. Exp., 2022)

Flexible task-DAG management in PHAST library: Data-parallel tasks and orchestration support for heterogeneous systems. - Biagio Peccerillo; Sandro Bartolini (Concurr. Comput. Pract. Exp., 2022)

Performance portability in a real world application: PHAST applied to Caffe. - Pablo Antonio Martínez; Biagio Peccerillo; Sandro Bartolini; José M. García 001; Gregorio Bernabé (Int. J. High Perform. Comput. Appl., 2022)

A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives. - Biagio Peccerillo; Mirco Mannino; Andrea Mondelli; Sandro Bartolini (J. Syst. Archit., 2022)

Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (CF, 2023)

Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2023)

IXIAM: ISA EXtension for Integrated Accelerator Management. - Biagio Peccerillo; Elham Cheshmikhani; Mirco Mannino; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2023)

Integration of RISC-V Page Table Walk in gem5 SE Mode. - Mirco Mannino; Yinting Huang; Biagio Peccerillo; Alessio Medaglini; Sandro Bartolini (RAPIDO@HiPEAC, 2024)

DeVAS: Decoupled Virtual Address Spaces. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (SBAC-PAD, 2024)

High-Performance Multi-Object Tracking for Autonomous Driving in Urban Scenarios With Heterogeneous Embedded Boards. - Alessio Medaglini; Biagio Peccerillo; Sandro Bartolini (IEEE Access, 2025)