Content Addressable Memory for Low-Power and High-Performance Applications. - Ataur R. Patwary; Bibiche M. Geuskens; Shih-Lien Lu (CSIE (3), 2009)

Resilient design in scaled CMOS for energy efficiency. - James W. Tschanz; Keith A. Bowman; Muhammad M. Khellah; Chris Wilkerson; Bibiche M. Geuskens; Dinesh Somasekhar; Arijit Raychowdhury; Jaydeep Kulkarni; Carlos Tokunaga; Shih-Lien Lu; Tanay Karnik; Vivek De (ASP-DAC, 2010)

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek De (CICC, 2010)

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. - Bibiche M. Geuskens; Muhammad M. Khellah; Jaydeep Kulkarni; Tanay Karnik; Vivek De (CICC, 2010)

Resilient microprocessor design for high performance & energy efficiency. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISLPED, 2010)

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. - Arijit Raychowdhury; Bibiche M. Geuskens; Jaydeep Kulkarni; James W. Tschanz; Keith A. Bowman; Tanay Karnik; Shih-Lien Lu; Vivek De; Muhammad M. Khellah (ISSCC, 2010)

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. - James W. Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISSCC, 2010)

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. - Arijit Raychowdhury; Jim Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek K. De (IEEE J. Solid State Circuits, 2011)

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. - Arijit Raychowdhury; Bibiche M. Geuskens; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Tanay Karnik; Muhammad M. Khellah; Vivek K. De (IEEE J. Solid State Circuits, 2011)

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. - Jaydeep Kulkarni; Bibiche M. Geuskens; Tanay Karnik; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2012)

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip. - Ahmed M. Eltawil; Michael Engel; Bibiche M. Geuskens; Amin Khajeh Djahromi; Fadi J. Kurdahi; Peter Marwedel; Smaïl Niar; Mazen A. R. Saghir (Microprocess. Microsystems, 2013)

A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. - Rinkle Jain; Bibiche M. Geuskens; Stephen T. Kim; Muhammad M. Khellah; Jaydeep Kulkarni; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2014)

16.1 A nanogap transducer array on 32nm CMOS for electrochemical DNA sequencing. - Drew A. Hall; Jonathan S. Daniels; Bibiche M. Geuskens; Noureddine Tayebi; Grace M. Credo; David J. Liu; Handong Li; Kai Wu; Xing Su; Madoo Varma; Oguz H. Elibol (ISSCC, 2016)