Physics-based compact modeling for nonclassical CMOS. - Vishal P. Trivedi; Jerry G. Fossum; Leo Mathew; Murshed M. Chowdhury; Weimin Zhang; Glenn O. Workman; Bich-Yen Nguyen (ICCAD, 2005)

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below. - Claire Fenouillet-Béranger; P. Perreau; S. Denorme; L. Tosti; François Andrieu; Olivier Weber; S. Barnola; C. Arvet; Y. Campidelli; Sébastien Haendler; R. Beneyton; C. Perrot; et al. (ESSCIRC, 2009)

FDSOI: From substrate to devices and circuit applications. - Carlos Mazure; Richard Ferrant; Bich-Yen Nguyen; Walter Schwarzenbach; Cécile Moulin (ESSCIRC, 2010)

SRAM design in fully-depleted SOI technology. - Borivoje Nikolic; Changhwan Shin; Min Hee Cho; Xin Sun; Tsu-Jae King Liu; Bich-Yen Nguyen (ISCAS, 2010)

32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit. - Olivier Thomas; Jean-Philippe Noel; Claire Fenouillet-Béranger; Marie-Anne Jaud; J. Dura; P. Perreau; Frédéric Boeuf; François Andrieu; D. Delprat; F. Boedt; Konstantin Bourdelle; Bich-Yen Nguyen; et al. (ISCAS, 2010)

Strained silicon on insulator substrates for fully depleted application. - Walter Schwarzenbach; N. Daval; S. Kerdilès; G. Chabanne; C. Figuet; S. Guerroudj; O. Bonnin; X. Cauchy; Bich-Yen Nguyen; Christophe Maleville (ICICDT, 2012)

3D monolithic integration: Stacking technology and applications. - Ionut Radu; Bich-Yen Nguyen; Gweltaz Gaudin; Carlos Mazure (ICICDT, 2015)

Layout engineering to suppress hysteresis of negative capacitance FinFET. - Eunah Ko; Jaesung Jo; Changhwan Shin; Bich-Yen Nguyen (ICICDT, 2017)

FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond. - Walter Schwarzenbach; Manuel Sellier; Bich-Yen Nguyen; Christophe Girard; Christophe Maleville (ICICDT, 2017)

Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs. - Yiming Qu; Ran Cheng; Wei Liu; Junkang Li; Bich-Yen Nguyen; Olivier Faynot; Nuo Xu; Bing Chen; Yi Zhao 015 (IRPS, 2018)

22FD-SOI Variability Improvement Thanks to SmartCut Thickness Control at Atomic Scale. - Walter Schwarzenbach; L. Loubriat; Vincent Joseph; Laurent Viravaux; Olivier Moreau; Sebastien Lasserre; Bich-Yen Nguyen (ESSDERC, 2019)

Low Temperature SmartCutTM enables High Density 3D SoC Applications. - Walter Schwarzenbach; Bich-Yen Nguyen; Guillaume Besnard (ICICDT, 2019)

Smart Cut™ technology: from Substrate Enginnering to Advanced 3D Integration. - Guillaume Besnard; Bich-Yen Nguyen; Christophe Maleville (ICICDT, 2022)

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. - A. Vandooren; N. Parihar; Jacopo Franco; Roger Loo; Hiroaki Arimura; R. Rodriguez; F. Sebaai; S. Iacovo; Kevin Vandersmissen; W. Li; G. Mannaert; D. Radisic; et al. (VLSI Technology and Circuits, 2022)

Non-Destructive-Read 1T1C Ferroelectric Capacitive Memory Cell with BEOL 3D Monolithically Integrated IGZO Access Transistor for 4F2 High-Density Integration. - Zuopu Zhou; Leming Jiao; Qiwen Kong; Zijie Zheng; Kaizhen Han; Yue Chen; Chen Sun 010; Bich-Yen Nguyen; Xiao Gong (VLSI Technology and Circuits, 2023)

Fluorine Plasma Treatment-Enabled ITO Transistors: Excellent Reliability and Comprehensive Understanding of Temperature Dependence from 77K to 375K. - Xuanqi Chen; Gan Liu; Wei Shi; Yuye Kang; Qiwen Kong; Yuxuan Wang; Rui Shao; Bich-Yen Nguyen; Gengchiau Liang; Kaizhen Han; Xiao Gong (VLSI Technology and Circuits, 2024)

Unveiling the Impact of AC PBTI on Hydrogen Formation in Oxide Semiconductor Transistors. - Gan Liu; Qiwen Kong; Zuopu Zhou; X. Ying; Chen Sun 010; Kaizhen Han; Yuye Kang; Dong Zhang; Xiaolin Wang 007; Yang Feng; Wei Shi; Bich-Yen Nguyen; et al. (VLSI Technology and Circuits, 2024)