Using Integer Equations for High Level Formal Verification Property Checking. - Bijan Alizadeh; Mohammad Reza Kakoee (ISQED, 2003)

Property Checking based on Hierarchical Integer Equations. - Bijan Alizadeh; Zainalabedin Navabi (ACSD, 2004)

Using Integer Equations to Check PSL Properties in RT Level Design. - Bijan Alizadeh; Zainalabedin Navabi (IWSOC, 2004)

Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. - Arash Hooshmand; Saeed Shamshiri; Mohammad Alisafaee; Bijan Alizadeh; Pejman Lotfi-Kamran; Mostafa Naderi; Zainalabedin Navabi (ISCAS (1), 2005)

Word level functional coverage computation. - Bijan Alizadeh (ASP-DAC, 2006)

Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. - Bijan Alizadeh; Masahiro Fujita (ATVA, 2007)

A novel formal approach to generate high-level test vectors without ILP and SAT solvers. - Bijan Alizadeh; Masahiro Fujita (HLDVT, 2007)

Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram. - Bijan Alizadeh; Masahiro Fujita (CSICC, 2008)

Arithmetic Circuits Verification without Looking for Internal Equivalences. - Omid Sarbishei; Bijan Alizadeh; Masahiro Fujita (MEMOCODE, 2008)

Polynomial datapath optimization using partitioning and compensation heuristics. - Omid Sarbishei; Bijan Alizadeh; Masahiro Fujita (DAC, 2009)

Modular arithmetic decision procedure with auto-correction mechanism. - Bijan Alizadeh; Masahiro Fujita (HLDVT, 2009)

Improved heuristics for finite word-length polynomial datapath optimization. - Bijan Alizadeh; Masahiro Fujita (ICCAD, 2009)

High-level optimization of integer multipliers over a finite bit-width with verification capabilities. - Omid Sarbishei; Mahmoud Tabandeh; Bijan Alizadeh; Masahiro Fujita (MEMOCODE, 2009)

A Unified Framework for Equivalence Verification of Datapath Oriented Applications. - Bijan Alizadeh; Masahiro Fujita (IEICE Trans. Inf. Syst., 2009)

A Formal Approach for Debugging Arithmetic Circuits. - Omid Sarbishei; Mahmoud Tabandeh; Bijan Alizadeh; Masahiro Fujita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Pipelined Microprocessors Optimization and Debugging. - Bijan Alizadeh; Amir Masoud Gharehbaghi; Masahiro Fujita (ARC, 2010)

Guided gate-level ATPG for sequential circuits using a high-level test generation approach. - Bijan Alizadeh; Masahiro Fujita (ASP-DAC, 2010)

Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). - Amir Masoud Gharehbaghi; Bijan Alizadeh; Masahiro Fujita (FPGA, 2010)

A debugging method for repairing post-silicon bugs of high performance processors in the fields. - Bijan Alizadeh; Masahiro Fujita (FPT, 2010)

Polynomial datapath optimization using constraint solving and formal modelling. - Finn Haedicke; Bijan Alizadeh; Görschwin Fey; Masahiro Fujita; Rolf Drechsler (ICCAD, 2010)

Modular Datapath Optimization and Verification Based on Modular-HED. - Bijan Alizadeh; Masahiro Fujita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. - Bijan Alizadeh; Mohammad Mirzaei; Masahiro Fujita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Modular equivalence verification of polynomial datapaths with multiple word-length operands. - Bijan Alizadeh; Masahiro Fujita (HLDVT, 2011)

Early case splitting and false path detection to improve high level ATPG techniques. - Bijan Alizadeh; Masahiro Fujita (ISCAS, 2011)

Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. - Bijan Alizadeh; Masahiro Fujita (ISQED, 2011)

A formal approach to debug polynomial datapath designs. - Bijan Alizadeh (ASP-DAC, 2012)

A functional test generation technique for RTL datapaths. - Bijan Alizadeh; Masahiro Fujita (HLDVT, 2012)

Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques. - Samaneh Ghandali; Bijan Alizadeh; Zainalabedin Navabi; Masahiro Fujita (MEMOCODE, 2012)

Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors. - Bijan Alizadeh (ACM Trans. Design Autom. Electr. Syst., 2012)

A probabilistic approach for counterexample generation to aid design debugging. - Payman Behnam; Hossein Sabaghian Bidgoli; Bijan Alizadeh; Kamyar Mohajerani; Zainalabedin Navabi (EWDTS, 2013)

A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. - Mohammad Mirzaei; Mahmoud Tabandeh; Bijan Alizadeh; Zainalabedin Navabi (IEEE Des. Test, 2013)

Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs. - Bijan Alizadeh; Payman Behnam (Microprocess. Microsystems, 2013)

Dynamic Flip-Flop conversion to tolerate process variation in low power circuits. - Mehrzad Nejat; Bijan Alizadeh; Ali Afzali-Kusha (DATE, 2014)

Automated formal approach for debugging dividers using dynamic specification. - Mohammad Hashem Haghbayan; Bijan Alizadeh; Amir-Mohammad Rahmani; Pasi Liljeberg; Hannu Tenhunen (DFT, 2014)

Automatic correction of certain design errors using mutation technique. - Payman Behnam; Bijan Alizadeh; Zainalabedin Navabi (ETS, 2014)

Improving polynomial datapath debugging with HEDs. - Somayeh Sadeghi Kohan; Payman Behnam; Bijan Alizadeh; Masahiro Fujita; Zainalabedin Navabi (ETS, 2014)

Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA. - Ehsan Qasemi; Amir Samadi; Mohammad H. Shadmehr; Bardia Azizian; Sajjad Mozaffari; Amir Shirian; Bijan Alizadeh (FPT, 2014)

RTL datapath optimization using system-level transformations. - Samaneh Ghandali; Bijan Alizadeh; Masahiro Fujita; Zainalabedin Navabi (ISQED, 2014)

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. - Farimah Farahmandi; Bijan Alizadeh; Zainalabedin Navabi (ISVLSI, 2014)

A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression. - Vahid Janfaza; Payman Behnam; Bahjat Forouzandeh; Bijan Alizadeh (ISVLSI, 2014)

Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism. - M. H. Haghbayan; Bijan Alizadeh; Payman Behnam; Saeed Safari (VLSID, 2014)

In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms. - Payman Behnam; Bijan Alizadeh (ATS, 2015)

Low power scheduling in high-level synthesis using dual-Vth library. - Samaneh Ghandali; Bijan Alizadeh; Zainalabedin Navabi (ISQED, 2015)

A Timing Error Mitigation Technique for High Performance Designs. - Mehrnaz Ahmadi; Bijan Alizadeh; Behjat Forouzandeh (ISVLSI, 2015)

Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. - Alireza Mahzoon; Bijan Alizadeh (ISVLSI, 2015)

Signature oriented model pruning to facilitate multi-threaded processors debugging. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (VTS, 2015)

UPF-based formal verification of low power techniques in modern processors. - Reza Sharafinejad; Bijan Alizadeh; Masahiro Fujita (VTS, 2015)

Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction. - Farimah Farahmandi; Bijan Alizadeh (Microprocess. Microsystems, 2015)

Analytical performance model for FPGA-based reconfigurable computing. - Hossein Mehri; Bijan Alizadeh (Microprocess. Microsystems, 2015)

A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. - Bijan Alizadeh; Payman Behnam; Somayeh Sadeghi Kohan (IEEE Trans. Computers, 2015)

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. - Samaneh Ghandali; Bijan Alizadeh; Masahiro Fujita; Zainalabedin Navabi (IEEE Trans. Computers, 2015)

Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations. - Mehrzad Nejat; Bijan Alizadeh; Ali Afzali-Kusha (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Formally analyzing fault tolerance in datapath designs using equivalence checking. - Payman Behnam; Bijan Alizadeh; Sajjad Taheri; Masahiro Fujita (ASP-DAC, 2016)

Combinational trace signal selection with improved state restoration for post-silicon debug. - Siamack BeigMohammadi; Bijan Alizadeh (DATE, 2016)

A dynamic specification to automatically debug and correct various divider circuits. - Mohammad Hashem Haghbayan; Bijan Alizadeh (Integr., 2016)

UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications. - Mahdieh Grailoo; Bijan Alizadeh; Behjat Forouzandeh (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models. - Hossein Mehri; Bijan Alizadeh (ACM Trans. Design Autom. Electr. Syst., 2016)

Systematic approximate logic optimization using don't care conditions. - Sahand Salamat; Mehrnaz Ahmadi; Bijan Alizadeh; Masahiro Fujita (ISQED, 2017)

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. - Hossein Sabaghian Bidgoli; Payman Behnam; Bijan Alizadeh; Zainalabedin Navabi (ISVLSI, 2017)

Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs. - Payman Behnam; Bijan Alizadeh; Sajjad Taheri (CoRR, 2017)

Improved Range Analysis in Fixed-Point Polynomial Data-Path. - Mahdieh Grailoo; Bijan Alizadeh; Behjat Forouzandeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations. - Mehrnaz Ahmadi; Bijan Alizadeh; Behjat Forouzandeh (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Systematic Design Space Exploration of Floating-Point Expressions on FPGA. - Alireza Mahzoon; Bijan Alizadeh (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications. - Shayan Moini; Bijan Alizadeh; Mohammad Emad; Reza Ebrahimpour (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis. - Mohammad Reza Azarbad; Bijan Alizadeh (ACM Trans. Design Autom. Electr. Syst., 2017)

OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. - Alireza Mahzoon; Bijan Alizadeh (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization. - Sahand Salamat; Mohammad Reza Azarbad; Bijan Alizadeh (ICRC, 2018)

QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations. - Bijan Alizadeh; Mehdi Shakeri (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Automatic Correction of Dynamic Power Management Architecture in Modern Processors. - Reza Sharafinejad; Bijan Alizadeh; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A New RF-PUF Based Authentication of Internet of Things Using Random Forest Classification. - Amir Ashtari; Ahmad Shabani; Bijan Alizadeh (ISCISC, 2019)

Data-path aware high-level ECO synthesis. - Masoud Shiroei; Bijan Alizadeh; Masahiro Fujita (Integr., 2019)

Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. - Bijan Alizadeh; Seyyed Reza Sharafinejad (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors. - Mojtaba Abbasnezhad; Bijan Alizadeh (IEEE Trans. Instrum. Meas., 2019)

A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs. - Mehrnaz Ahmadi; Sahand Salamat; Bijan Alizadeh (IEEE Trans. Very Large Scale Integr. Syst., 2019)

PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices. - Ahmad Shabani; Bijan Alizadeh (J. Netw. Comput. Appl., 2020)

Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug. - Siamack BeigMohammadi; Bijan Alizadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability. - Ahmad Shabani; Bijan Alizadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits. - Bijan Alizadeh; Yasaman Abadi (IEEE Trans. Circuits Syst., 2020)

FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network. - Ali Azarmi Gilan; Mohammad Emad; Bijan Alizadeh (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation. - Negar Aghapour Sabbagh; Bijan Alizadeh (ETS, 2021)

FPGA-based Implementation of a New Data Frame Correction System for Merging Units. - Mohammad Hashemi; Bijan Alizadeh (CoRR, 2021)

SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis. - Mohammad Sabri Abrebekoh; Ahmad Shabani; Bijan Alizadeh (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Enhancing Hardware Trojan Detection Sensitivity Using Partition-Based Shuffling Scheme. - Ahmad Shabani; Bijan Alizadeh (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices. - Amir Ashtari; Ahmad Shabani; Bijan Alizadeh (ISC Int. J. Inf. Secur., 2022)

Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme. - Fatemeh Khormizi; Ahmad Shabani; Bijan Alizadeh (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A comparative study of machine learning classifiers for secure RF-PUF-based authentication in internet of things. - Amir Ashtari; Ahmad Shabani; Bijan Alizadeh (Microprocess. Microsystems, 2022)

Automatic correction of RTL designs using a lightweight partial high level synthesis. - Bijan Alizadeh; Masoud Shiroei (Integr., 2023)

DC-PUF: Machine learning-resistant PUF-based authentication protocol using dependency chain for resource-constraint IoT devices. - Abolfazl Sajadi; Ahmad Shabani; Bijan Alizadeh (J. Netw. Comput. Appl., 2023)

An FPGA-Based Hardware Architecture for P + M Class PMU Using Accuracy-Aware O-Spline Filter Selection and Modulation Detection. - Ali Falahati; Mahdieh Shamirzaee; Bijan Alizadeh (IEEE Trans. Instrum. Meas., 2024)

Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification. - Negar Aghapour Sabbagh; Bijan Alizadeh (ACM Trans. Design Autom. Electr. Syst., 2024)

Systematic Trojan Detection in Crypto-Systems Using the Model Checker. - Hamed Hossein-Talaee; Ali Jahanian 001; Bijan Alizadeh (J. Circuits Syst. Comput., 2024)

Concealing Exposed Circuit Features Through a MaxSAT-Based Logic Locking Method. - Mohammad Moradi Shahmiri; Bijan Alizadeh (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FPGA-based CNN accelerator using Convolutional Processing Element to reduce idle states. - Mohammad Dehnavi; Aran Ghasemi; Bijan Alizadeh (J. Syst. Archit., 2025)

AILIS: effective hardware accelerator for incremental learning with intelligent selection in classification. - Nafiseh HosseinpourFardi; Bijan Alizadeh (J. Supercomput., 2025)

Localizing Multiple Bugs in RTL Designs by Classifying Hit-Statements Using Neural Networks. - Mahsa Heidari; Bijan Alizadeh (IEEE Trans. Computers, 2025)

FixRTL: Auto-correction of Multiple RTL Bugs by a New Feature Burst Clustering Algorithm and Mutation. - Mahsa Heidari; Bijan Alizadeh (ACM Trans. Design Autom. Electr. Syst., 2025)