A half-micron CMOS logic generation. - Charles W. Koburger III; William F. Clark; James W. Adkisson; Eric Adler; Paul E. Bakeman; Albert S. Bergendahl; Alan B. Botula; W. Chang; Bijan Davari; John H. Givens; Howard H. Hansen; Steven J. Holmes; et al. (IBM J. Res. Dev., 1995)

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. - Ghavam G. Shahidi; James D. Warnock; James Comfort; Stephen E. Fischer; Patricia A. McFarland; Alexandre Acovic; Terry I. Chappell; Barbara A. Chappell; Tak H. Ning; Carl J. Anderson; Robert H. Dennard; Jack Y.-C. Sun; et al. (IBM J. Res. Dev., 1995)

CMOS scaling for high performance and low power-the next ten years. - Bijan Davari; Robert H. Dennard; Ghavam G. Shahidi (Proc. IEEE, 1995)

A 480-MHz RISC microprocessor in a 0.12-μm Leff CMOS technology with copper interconnects. - Chekib Akrout; John Bialas; Miles G. Canada; Duane Cawthron; James Corr; Bijan Davari; Robert Floyd 002; Stephen F. Geissler; Ronald Goldblatt; Robert Houle; Paul Kartschoke; Diane Kramer; et al. (IEEE J. Solid State Circuits, 1998)

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. - Osamu Takahashi; Sang H. Dhong; Manabu Ohkubo; Shohji Onishi; Robert H. Dennard; Robert Hannon; Scott Crowder; Subramanian S. Iyer; Matthew R. Wordeman; Bijan Davari; William B. Weinberger; Naoaki Aoki (IEEE J. Solid State Circuits, 2000)

Workload and network-optimized computing systems. - David P. LaPotin; Shahrokh Daijavad; Charles L. Johnson; Steven W. Hunter; Kazuaki Ishizaki; Hubertus Franke; Heather D. Achilles; Dan P. Dumarot; Nancy A. Greco; Bijan Davari (IBM J. Res. Dev., 2010)