A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. - Biju K. Raveendran; Sundar Balasubramaniam; K. Durga Prasad; S. Gurunarayanan 001 (Asia-Pacific Computer Systems Architecture Conference, 2006)

Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems. - Biju K. Raveendran; K. Durga Prasad; Sundar Balasubramaniam; S. Gurunarayanan 001 (ICDCN, 2006)

EFFS: Efficient Flash File System for Wireless Sensor Nodes. - Biju K. Raveendran; Janardan Prasad Misra; Karan Bhatnagar; S. Gurunarayanan 001 (ESA, 2007)

An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System. - Biju K. Raveendran; T. S. B. Sudarshan; Avinash Patil; Komal B. Randive; S. Gurunarayanan 001 (ESA, 2007)

Evaluation of priority based real time scheduling algorithms: choices and tradeoffs. - Biju K. Raveendran; Sundar Balasubramaniam; S. Gurunarayanan 001 (SAC, 2008)

Simulation based Performance Study of Cache Coherence Protocols. - Neethu Bal Mallya; Geeta Patil; Biju K. Raveendran (iNIS, 2015)

Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. - Neethu Bal Mallya; Geeta Patil; Biju K. Raveendran (VLSID, 2015)

DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems. - Shubhangi K. Gawali; Biju K. Raveendran (CoDIT, 2016)

DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems. - Kajal Varma; Geeta Patil; Biju K. Raveendran (VLSID, 2017)

eduCloud: a VM communication aware, migration efficient cloud for scientific computing. - Biju K. Raveendran; Pravin Joshi; Sahil Mittal (Int. J. Commun. Networks Distributed Syst., 2017)

Energy efficient real-time scheduling algorithm for mixed task set on multi-core processors. - Mayuri Digalwar; Praveen Gahukar; Biju K. Raveendran; Sudeept Mohan (Int. J. Embed. Syst., 2017)

LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors. - Mayuri Digalwar; Biju K. Raveendran; Sudeept Mohan (Sustain. Comput. Informatics Syst., 2017)

SMILEY: A Mixed-Criticality Real-Time Task Scheduler for Multicore Systems. - Alen Sabu; Biju K. Raveendran; Rituparna Ghosh (DS-RT, 2018)

MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems. - Arun S. Nair; Louella Mesquita Colaco; Geeta Patil; Biju K. Raveendran; Sasikumar Punnekkat (DS-RT, 2019)

DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems. - Shubhangi K. Gawali; Biju K. Raveendran (Int. J. Embed. Syst., 2019)

MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation. - Geeta Patil; Neethu Bal Mallya; Biju K. Raveendran (Int. J. Embed. Syst., 2019)

MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache. - Arun S. Nair; Aboli Vijayan Pai; Biju K. Raveendran; Geeta Patil (DS-RT, 2021)

pmcEDF: An Energy Efficient Procrastination Scheduler for Multi-core Mixed Criticality Systems. - Louella Colaco; Amol Pai; Biju K. Raveendran; Sasikumar Punnekkat (HPCC/DSS/SmartCity/DependSys, 2021)

Task models for mixed criticality systems - a review. - Louella Colaco; Arun S. Nair; Biju K. Raveendran; Sasikumar Punnekkat (Int. J. Crit. Comput. Based Syst., 2023)

SACRED: Software Approach for Collaboration and Research Dissemination. - Louella Colaco; Arun S. Nair; Anurag Madnawat; Biju K. Raveendran (Int. J. e Collab., 2023)

mcDVFS: cycle conserving DVFS scheduler for multi-core mixed criticality systems. - Louella Colaco; Prashiksha Jain; Arun S. Nair; Biju K. Raveendran; Sasikumar Punnekkat (Int. J. Parallel Emergent Distributed Syst., 2023)

CAMP: a hierarchical cache architecture for multi-core mixed criticality processors. - Arun S. Nair; Geeta Patil; Archit Agarwal; Aboli Vijayan Pai; Biju K. Raveendran; Sasikumar Punnekkat (Int. J. Parallel Emergent Distributed Syst., 2024)