A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. - Bill Pontikakis; Mohamed Nekili (ISCAS (5), 2002)

Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. - Bill Pontikakis; François R. Boyer; Yvon Savaria (IWSOC, 2005)

A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. - Bill Pontikakis; François R. Boyer; Yvon Savaria (ISCAS, 2006)

A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. - Bill Pontikakis; Hung Tien Bui; François R. Boyer; Yvon Savaria (ISCAS, 2007)

An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs). - Syed Rafay Hasan; Bill Pontikakis; Yvon Savaria (ISCAS, 2009)

An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. - Mengyue Su; Jean-Pierre David; Yvon Savaria; Bill Pontikakis; Thomas Luinaud (ISCAS, 2022)

A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. - Mostafa Elbediwy; Bill Pontikakis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2023)

DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue. - Mostafa Elbediwy; Bill Pontikakis; Alireza Ghaffari; Jean-Pierre David; Yvon Savaria (IEEE Trans. Netw. Serv. Manag., 2024)

5G Fronthaul in Modular P4: eCPRI Protocol Processing and Precise BMv2 Timestamps for PTP-1588. - Atabak Nojavan; Bill Pontikakis; François-Raymond Boyer; Yvon Savaria (IEEE Access, 2025)

P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications. - Mohsen Rahmati; François-Raymond Boyer; Bill Pontikakis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2025)