Correlating Testability with Fault Detection. - Bill Underwood; M. Ray Mercer (ITC, 1984)

Built-In Self Test Input Generator for Programmable Logic Arrays. - John Salick; Bill Underwood; M. Ray Mercer (ITC, 1985)

Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. - Rhonda Kay Gaede; M. Ray Mercer; Bill Underwood (ITC, 1986)

An Analysis of Parallel Logic Simulation on Several Architectures. - Steven P. Smith; Bill Underwood; Joe Newman (ICPP (1), 1988)

D^3FS: A Demand Driven Deductive Fault Simulator. - Steven P. Smith; Bill Underwood; M. Ray Mercer (ITC, 1988)

The Parallel-Test-Detect Fault Simulation Algorithm. - Bill Underwood; Jack Ferguson (ITC, 1989)

The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. - Thomas W. Williams; Bill Underwood; M. Ray Mercer (DAC, 1991)

Delay Testing Quality in Timing-Optimized Designs. - Eun Sei Park; Bill Underwood; Thomas W. Williams; M. Ray Mercer (ITC, 1991)

Path-Delay Fault Simulation for a Standard Scan Design Methodology. - Sungho Kang; Wai-On Law; Bill Underwood (ICCD, 1994)

Fastpath: A Path-Delay Test Generator for Standard Scan Designs. - Bill Underwood; Wai-On Law; Sungho Kang; Haluk Konuk (ITC, 1994)

Speed Binning with Path Delay Test in 150-nm Technology. - Bruce Cory; Rohit Kapur; Bill Underwood (IEEE Des. Test Comput., 2003)