A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0. - Anant S. Kamath; Biman Chattopadhyay; Gopalkrishna Nayak (CICC, 2009)

A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth. - Anant S. Kamath; Biman Chattopadhyay (ISCAS, 2010)

A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS. - Biman Chattopadhyay; Anant S. Kamath; Satyasai Evani; Karthik Subburaj (CICC, 2011)

A 1.8GHz Digital PLL in 65nm CMOS. - Biman Chattopadhyay; Anant S. Kamath; Gopalkrishna Nayak (VLSI Design, 2011)

A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process. - Ravi Mehta; Sumantra Seth; Siddharth Shashidharan; Biman Chattopadhyay; Sujoy Chakravarty (ESSCIRC, 2012)

A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS. - Anant S. Kamath; Biman Chattopadhyay (ISCAS, 2012)

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. - Krishnaswamy Nagaraj; Anant S. Kamath; Karthik Subburaj; Biman Chattopadhyay; Gopalkrishna Nayak; Satyasai Evani; Neeraj P. Nayak; Indu Prathapan; Frank Zhang; Baher Haroun (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. - Jayesh Wadekar; Biman Chattopadhyay; Ravi Mehta; Gopalkrishna Nayak (VLSID, 2016)

A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. - Biman Chattopadhyay; Sharath N. Bhat; Gopalkrishna Nayak; Ravi Mehta (VLSID, 2018)