Bin Liu

Affiliations:
  • University of California, Los Angeles, CA, USA (PhD 2012)


According to our database1, Bin Liu authored at least 19 papers between 2009 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
Multithreaded pipeline synthesis for data-parallel kernels.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
SDC-based modulo scheduling for pipeline synthesis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
High-Level Synthesis for Nanoscale Integrated Circuits.
PhD thesis, 2012

A Study on the Impact of Compiler Optimizations on High-Level Synthesis.
Proceedings of the Languages and Compilers for Parallel Computing, 2012

Towards layout-friendly high-level synthesis.
Proceedings of the International Symposium on Physical Design, 2012

Combining module selection and replication for throughput-driven streaming programs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A metric for layout-friendly microarchitecture optimization in high-level synthesis.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Compilation and architecture support for customized vector instruction extension.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Automatic memory partitioning and scheduling for throughput and power optimization.
ACM Trans. Design Autom. Electr. Syst., 2011

High-Level Synthesis for FPGAs: From Prototyping to Deployment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2010

Accelerating Monte Carlo based SSTA using FPGA.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Coordinated resource optimization in behavioral synthesis.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Behavior-level observability don't-cares and application to low-power behavioral synthesis.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Scheduling with soft constraints.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Revisiting bitwidth optimizations.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization.
Proceedings of the FCCM 2009, 2009

A variation-tolerant scheduler for better than worst-case behavioral synthesis.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009


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