A variation-tolerant scheduler for better than worst-case behavioral synthesis. - Jason Cong; Albert Liu; Bin Liu 006 (CODES+ISSS, 2009)

Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. - Jason Cong; Karthik Gururaj; Bin Liu 006; Chunyue Liu; Zhiru Zhang; Sheng Zhou; Yi Zou (FCCM, 2009)

Revisiting bitwidth optimizations. - Jason Cong; Karthik Gururaj; Bin Liu 006; Chunyue Liu; Yi Zou; Zhiru Zhang; Sheng Zhou (FPGA, 2009)

Scheduling with soft constraints. - Jason Cong; Bin Liu 006; Zhiru Zhang (ICCAD, 2009)

Behavior-level observability don't-cares and application to low-power behavioral synthesis. - Jason Cong; Bin Liu 006; Zhiru Zhang (ISLPED, 2009)

Coordinated resource optimization in behavioral synthesis. - Jason Cong; Bin Liu 006; Junjuan Xu (DATE, 2010)

Accelerating Monte Carlo based SSTA using FPGA. - Jason Cong; Karthik Gururaj; Wei Jiang 035; Bin Liu 006; Kirill Minkovich; Bo Yuan; Yi Zou (FPGA, 2010)

Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. - Jason Cong; Bin Liu 006; Rupak Majumdar; Zhiru Zhang (ACM Trans. Design Autom. Electr. Syst., 2010)

High-Level Synthesis for FPGAs: From Prototyping to Deployment. - Jason Cong; Bin Liu 006; Stephen Neuendorffer; Juanjo Noguera; Kees A. Vissers; Zhiru Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Automatic memory partitioning and scheduling for throughput and power optimization. - Jason Cong; Wei Jiang 035; Bin Liu 006; Yi Zou (ACM Trans. Design Autom. Electr. Syst., 2011)

Compilation and architecture support for customized vector instruction extension. - Jason Cong; Mohammad Ali Ghodrat; Michael Gill; Hui Huang 001; Bin Liu 006; Raghu Prabhakar; Glenn Reinman; Marco Vitanza (ASP-DAC, 2012)

A metric for layout-friendly microarchitecture optimization in high-level synthesis. - Jason Cong; Bin Liu 006 (DAC, 2012)

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. - Yu-Ting Chen 003; Jason Cong; Hui Huang 001; Bin Liu 006; Chunyue Liu; Miodrag Potkonjak; Glenn Reinman (DATE, 2012)

Combining module selection and replication for throughput-driven streaming programs. - Jason Cong; Muhuan Huang; Bin Liu 006; Peng Zhang 007; Yi Zou (DATE, 2012)

Towards layout-friendly high-level synthesis. - Jason Cong; Bin Liu 006; Guojie Luo; Raghu Prabhakar (ISPD, 2012)

A Study on the Impact of Compiler Optimizations on High-Level Synthesis. - Jason Cong; Bin Liu 006; Raghu Prabhakar; Peng Zhang 007 (LCPC, 2012)

High-Level Synthesis for Nanoscale Integrated Circuits. - Bin Liu 006 (2012)

SDC-based modulo scheduling for pipeline synthesis. - Zhiru Zhang; Bin Liu 006 (ICCAD, 2013)

Multithreaded pipeline synthesis for data-parallel kernels. - Mingxing Tan; Bin Liu 006; Steve Dai; Zhiru Zhang (ICCAD, 2014)