Sleep transistor sizing using timing criticality and temporal currents. - Anand Ramalingam; Bin Zhang 011; Anirudh Devgan; David Z. Pan (ASP-DAC, 2005)

BulletProof: a defect-tolerant CMP switch architecture. - Kypros Constantinides; Stephen Plaza; Jason A. Blome; Bin Zhang 011; Valeria Bertacco; Scott A. Mahlke; Todd M. Austin; Michael Orshansky (HPCA, 2006)

Analytical modeling of SRAM dynamic stability. - Bin Zhang 011; Ari Arapostathis; Sani R. Nassif; Michael Orshansky (ICCAD, 2006)

FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. - Bin Zhang 011; Wei-Shen Wang; Michael Orshansky (ISQED, 2006)

Architecting a reliable CMP switch architecture. - Kypros Constantinides; Stephen Plaza; Jason A. Blome; Valeria Bertacco; Scott A. Mahlke; Todd M. Austin; Bin Zhang 011; Michael Orshansky (ACM Trans. Archit. Code Optim., 2007)

Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. - Bin Zhang 011; Michael Orshansky (ISQED, 2008)

Online circuit reliability monitoring. - Bin Zhang 011 (ACM Great Lakes Symposium on VLSI, 2009)