Inverse-Geometry Dependence of MOS Transistor Electrical Parameters. - M. C. Hsu; Bing J. Sheu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Knowledge-based analog circuit synthesis with flexible architecture. - Antony H. Fung; David J. Chen; Ying-Nan Lai; Bing J. Sheu (ICCD, 1988)

An investigation on local minima of a Hopfield network for optimization circuits. - Bang W. Lee; Bing J. Sheu (ICNN, 1988)

An MOS transistor charge model for VLSI design. - Bing J. Sheu; Wen-Jay Hsu; P. K. Ko (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Device and circuit simulation interface for an integrated VLSI design environment. - Chung-Ping Wan; Bing J. Sheu; Shih-Lien Lu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Characterization of GaAs MESFET gate capacitances. - Chih-Ching Shih; Bing J. Sheu; Huy M. Le (IEEE J. Solid State Circuits, 1988)

SLAM: a smart analog module layout generator for mixed analog-digital VLSI design. - David J. Chen; Ji-Chien Lee; Bing J. Sheu (ICCD, 1989)

Digital and analog integrated-circuit design with built-in reliability. - Wen-Jay Hsu; Bing J. Sheu; Vance C. Tyree (ICCD, 1989)

Temperature dependence modeling for MOS VLSI circuit simulation. - Chung-Ping Wan; Bing J. Sheu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

An integrated-circuit reliability simulator-RELY. - Bing J. Sheu; Wen-Jay Hsu; Bang W. Lee (IEEE J. Solid State Circuits, 1989)

Design of a neural-based A/D converter using modified Hopfield network. - Bang W. Lee; Bing J. Sheu (IEEE J. Solid State Circuits, 1989)

Automatic layout generation for mixed analog-digital VLSI neural chips. - David J. Chen; Bing J. Sheu (ICCD, 1990)

Real-time computing of optical flow using adaptive VLSI neuroprocessors. - Wai-Chi Fang; Bing J. Sheu; Ji-Chien Lee (ICCD, 1990)

Parallel digital image restoration using adaptive VLSI neural chips. - Ji-Chien Lee; Bing J. Sheu (ICCD, 1990)

VLSI image processor using analog programmable synapses and neurons. - Bang W. Lee; Ji-Chien Lee; Bing J. Sheu (IJCNN, 1990)

A high slew-rate CMOS amplifier for analog signal processing. - Bang W. Lee; Bing J. Sheu (IEEE J. Solid State Circuits, 1990)

A Neural Network Based VLSI Vector Quantizer for Real-Time Image Compression. - Wai-Chi Fang; Bing J. Sheu; Oscal T.-C. Chen (Data Compression Conference, 1991)

A VLSI neuroprocessor for real-time image flow computing. - Wai-Chi Fang; Bing J. Sheu; Ji-Chien Lee (ICASSP, 1991)

Real-time high-ratio image compression using adaptive VLSI neuroprocessors. - Bing J. Sheu; Wai-Chi Fang (ICASSP, 1991)

A GaAs Receiver Module for Optoelectronic Computing and Interconnection. - Joongho Choi; Bing J. Sheu (ICCD, 1991)

Testing of Analog Neural Array-Processor Chips. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda (ICCD, 1991)

Modified Hopfield neural networks for retrieving the optimal solution. - Bang W. Lee; Bing J. Sheu (IEEE Trans. Neural Networks, 1991)

Design of reliable VLSI circuits using simulation techniques. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda (IEEE J. Solid State Circuits, 1991)

An Adaptive High-Speed Lossy Data Compression. - Oscal T.-C. Chen; Zhen Zhang 010; Bing J. Sheu (Data Compression Conference, 1992)

Design of a multiprocessor DSP chip for flexible information processing. - Chia-Fen Chang; Bing J. Sheu; Hiroto Okada (ICASSP, 1992)

Adaptive vector quantizer for image compression using self-organization approach. - Oscal T.-C. Chen; Bing J. Sheu; Wai-Chi Fang (ICASSP, 1992)

Image Compression on a VLSI Neural-Based Vector Quantizer. - Oscal T.-C. Chen; Bing J. Sheu; Wai-Chi Fang (Inf. Process. Manag., 1992)

A mixed-signal VLSI neuroprocessor for image restoration. - Ji-Chien Lee; Bing J. Sheu; Joongho Choi; Ramalingam Chellappa (IEEE Trans. Circuits Syst. Video Technol., 1992)

A VLSI neural processor for image data compression using self-organization networks. - Wai-Chi Fang; Bing J. Sheu; Oscal T.-C. Chen; Joongho Choi (IEEE Trans. Neural Networks, 1992)

Advanced integrated-circuit reliability simulation including dynamic stress effects. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda; Chang-Gyu Hwang (IEEE J. Solid State Circuits, 1992)

General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons. - Bang W. Lee; Bing J. Sheu (IEEE J. Solid State Circuits, 1992)

A programmable analog VLSI neural network processor for communication receivers. - Joongho Choi; Sa Hyun Bang; Bing J. Sheu (IEEE Trans. Neural Networks, 1993)

Paralleled hardware annealing for optimal solutions on electronic neural networks. - Bang W. Lee; Bing J. Sheu (IEEE Trans. Neural Networks, 1993)

VLSI neuroprocessors for video motion detection. - Ji-Chien Lee; Bing J. Sheu; Wai-Chi Fang; Rama Chellappa (IEEE Trans. Neural Networks, 1993)

A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture. - Ji-Chien Lee; Bing J. Sheu; Rama Chellappa (J. VLSI Signal Process., 1993)

A mixed-signal VLSI competitive neuroprocessor for video motion detection. - Ji-Chien Lee; Bing J. Sheu; Rama Chellappa (J. VLSI Signal Process., 1993)

Design and characterization of analog VLSI neural network modules. - Sudhir M. Gowda; Bing J. Sheu; Joongho Choi; Chang-Gyu Hwang; James S. Cable (IEEE J. Solid State Circuits, 1993)

A high-precision VLSI winner-take-all circuit for self-organizing neural networks. - Joongho Choi; Bing J. Sheu (IEEE J. Solid State Circuits, 1993)

Search of Optimal Solutions in Multi-Level Neural Networks. - Sa Hyun Bang; Bing J. Sheu; Josephine C.-F. Chang (ISCAS, 1994)

An Analog MOS Model for Circuit Simulation and Benchmark Test Results. - Robert Chen-Hao Chang; Bing J. Sheu (ISCAS, 1994)

BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. - Sudhir M. Gowda; Bing J. Sheu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Image compression using self-organization networks. - Oscal T.-C. Chen; Bing J. Sheu; Wai-Chi Fang (IEEE Trans. Circuits Syst. Video Technol., 1994)

An adaptive vector quantizer based on the Gold-Washing method for image compression. - Oscal T.-C. Chen; Bing J. Sheu; Zhen Zhang 010 (IEEE Trans. Circuits Syst. Video Technol., 1994)

A Gaussian synapse circuit for analog VLSI neural networks. - Joongho Choi; Bing J. Sheu; Josephine C.-F. Chang (IEEE Trans. Very Large Scale Integr. Syst., 1994)

VLSI systolic binary tree-searched vector quantizer for image compression. - Wai-Chi Fang; Chi-Yung Chang; Bing J. Sheu; Oscal T.-C. Chen; John C. Curlander (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Testing of programmable analog neural network chips. - Sudhir M. Gowda; Bing J. Sheu; Wen-Jay Hsu (J. VLSI Signal Process., 1994)

A monolithic GaAs receiver for optical interconnect systems. - Joongho Choi; Bing J. Sheu; Oscal T.-C. Chen (IEEE J. Solid State Circuits, 1994)

VLSI design of densely-connected array processors. - Eric Y. Chou; Bing J. Sheu; Tony H. Wu; Robert C. Chang (ICCD, 1995)

Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. - Wai-Chi Fang; Bing J. Sheu; Holger Venus; Rainer Sandau (ICCD, 1995)

A compact VLSI design for recursive neural networks with hardware annealing capability. - Eric Y. Chou; Bing J. Sheu; Steve H. Jen (ICNN, 1995)

A hippocampal model implementation using VLSI table-look-up and model-based approaches. - Richard H. Tsai; Eric Y. Chou; Bing J. Sheu; Theodore W. Berger (ICNN, 1995)

Constructing Intelligent Microsystems with Modular VLSI Networks Design. - Bing J. Sheu (ISCAS, 1995)

VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities. - Bing J. Sheu; Sa Hyun Bang; Wai-Chi Fang (ISCAS, 1995)

VLSI Neural Network Implementation of a Hippocampal Model. - Bing J. Sheu; Theodore W. Berger; Tony H. Wu; Richard H. Tsai (ISCAS, 1995)

VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization. - Bing J. Sheu; Robert C. Chang; Tony H. Wu; Sa Hyun Bang (ISCAS, 1995)

A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication. - David C. Chen 001; Bing J. Sheu; Theodore W. Berger (ICCD, 1996)

A neural network communication equalizer with optimized solution capability. - David C. Chen 001; Bing J. Sheu; Eric Y. Chou (ICNN, 1996)

VLSI design for real-time signal processing based on biologically realistic neural models. - Richard H. Tsai; Bing J. Sheu; Theodore W. Berger (ICNN, 1996)

Optimal solutions for cellular neural networks by paralleled hardware annealing. - Sa Hyun Bang; Bing J. Sheu; Tony H. Wu (IEEE Trans. Neural Networks, 1996)

A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. - Wai-Chi Fang; Guang Yang 003; Bedabrata Pain; Bing J. Sheu (ICCD, 1997)

A CDMA communication detector with robust near-far resistance using paralleled array processors. - David Cheng-Hsiung Chen; Bing J. Sheu; Wayne C. Young (IEEE Trans. Circuits Syst. Video Technol., 1997)

Guest Editorial. - Bing J. Sheu; Mohammed Ghanbari 001; Horng-Dar Lin; Chung-Yu Wu (IEEE Trans. Circuits Syst. Video Technol., 1997)

Advances in efficient optical links to enhance desktop multimedia processor systems. - Richard H. Tsai; Bing J. Sheu; Andrew Kostrzewski; Jeongdal Kim (IEEE Trans. Circuits Syst. Video Technol., 1997)

A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs. - Steve H. Jen; Bing J. Sheu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's. - Steve H. Jen; Bing J. Sheu; Yoondong Park 001 (IEEE J. Solid State Circuits, 1999)

Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses. - Alex Yoondong Park; Jim-Shih Liaw; Theodore W. Berger; Bing J. Sheu (IJCNN (4), 2000)

Panel: Is Nanometer Design Under Control? - Andrew B. Kahng; Bing J. Sheu; Nancy Nettleton; John M. Cohn; Shekhar Borkar; Louis Scheffer; Ed Cheng; Sang Wang (DAC, 2001)

Brain-implantable biomimetic electronics as the next era in neural prosthetics. - Theodore W. Berger; Michel Baudry; Roberta Diaz Brinton; Jim-Shih Liaw; Vasilis Z. Marmarelis; Alex Yoondong Park; Bing J. Sheu; Armand R. Tanguay (Proc. IEEE, 2001)

An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. - Alex Yoondong Park; Steve H. Jen; Bing J. Sheu; Heesook Yoon; In Gyeom Kim (ISCAS (5), 2002)

Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs? - P. Yue; Bing J. Sheu; A. Matsuzawa; K. Asada; L. Loh; Kofi A. A. Makinwa; Shekhar Borkar; Vladimir Stojanovic (VLSIC, 2015)

Reinforcement Learning-Based Complete Area Coverage Path Planning for a Modified hTrihex Robot. - Koppaka Ganesh Sai Apuroop; Anh Vu Le; Mohan Rajesh Elara; Bing J. Sheu (Sensors, 2021)

Adaptive Floor Cleaning Strategy by Human Density Surveillance Mapping with a Reconfigurable Multi-Purpose Service Robot. - Vinu Sivanantham; Anh Vu Le; Yuyao Shi; Mohan Rajesh Elara; Bing J. Sheu (Sensors, 2021)