Bing Li

Orcid: 0000-0003-0732-2267

Affiliations:

Duke University, Durham, NC, USA
Chinese Academy of Sciences, Institute of Computing Technology, Key Laboratory of Computer System and Architecture, Beijing, China (former)

According to our database¹, Bing Li authored at least 25 papers between 2013 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

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Bibliography

2023

A Coordinated Model Pruning and Mapping Framework for RRAM-Based DNN Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

An Automated Quantization Framework for High-Utilization RRAM-Based PIM.

[BibT_eX]

[DOI]

Bing Li

Songyun Qu

Ying Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

FeFET-based Process-in-Memory Architecture for Low-Power DNN Training.

[BibT_eX]

[DOI]

Farzaneh Zokaee

Bing Li

Fan Chen

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

2020

RED: A ReRAM-Based Efficient Accelerator for Deconvolutional Computation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks.

[BibT_eX]

[DOI]

Bing Li

Janardhan Rao Doppa

Partha Pratim Pande

Krishnendu Chakrabarty

Joe X. Qiu

Hai (Helen) Li

ACM J. Emerg. Technol. Comput. Syst., 2020

A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Thread Batching for High-performance Energy-efficient GPU Memory Design.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

PUFPass: A password management mechanism based on software/hardware codesign.

[BibT_eX]

[DOI]

Integr., 2019

Resistive Memory-Based In-Memory Computing: From Device and Large-Scale Integration System Perspectives.

[BibT_eX]

[DOI]

Adv. Intell. Syst., 2019

Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications.

[BibT_eX]

[DOI]

Bing Li

Bonan Yan

Hai Li

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

RED: A ReRAM-based Deconvolution Accelerator.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Build reliable and efficient neuromorphic design with memristor technology.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Exploration of Automatic Mixed-Precision Search for Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018

Design and Data Management for Magnetic Racetrack Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

ReRAM-based accelerator for deep learning.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Running sparse and low-precision neural network: When algorithm meets hardware.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Power-Utility-Driven Write Management for MLC PCM.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2017

2014

Short-SET: An energy-efficient write scheme for MLC PCM.

[BibT_eX]

[DOI]

Bing Li

Yu Hu

Xiaowei Li

Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Partial-SET: Write speedup of PCM main memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Tolerating Noise in MLC PCM with Multi-Bit Error Correction Code.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Bing Li

Timeline

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