Supporting Multimedia Applications in Home Networks using SIP and SLP. - Min-Xiou Chen; Bing-Yang Lin; Wen-Yen Weng (DCNET/OPTICS, 2010)

A Memory Failure Pattern Analyzer for memory diagnosis and repair. - Bing-Yang Lin; Mincent Lee; Cheng-Wen Wu (VTS, 2012)

Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. - Bing-Yang Lin; Mincent Lee; Cheng-Wen Wu (Asian Test Symposium, 2013)

Redundancy architectures for channel-based 3D DRAM yield improvement. - Bing-Yang Lin; Wan-Ting Chiang; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2014)

Location service and session mobility for streaming media applications in home networks. - Min-Xiou Chen; Bing-Yang Lin (Comput. Stand. Interfaces, 2014)

On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. - Chun-Chuan Chi; Bing-Yang Lin; Cheng-Wen Wu; Min-Jer Wang; Hung-Chih Lin; Ching-Nen Peng (IEEE Des. Test, 2014)

System-level test coverage prediction by structural stress test data mining. - Bing-Yang Lin; Cheng-Wen Wu; Harry H. Chen (VLSI-DAT, 2015)

Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test. - Hsuan-Wei Liu; Bing-Yang Lin; Cheng-Wen Wu (ATS, 2016)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. - Yu-Chieh Huang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (DAC, 2016)

A fast sweep-line-based failure pattern extractor for memory diagnosis. - Sin-Yu Wei; Bing-Yang Lin; Cheng-Wen Wu (ETS, 2016)

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. - Bing-Yang Lin; Wan-Ting Chiang; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2016)

A Local Parallel Search Approach for Memory Failure Pattern Identification. - Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Trans. Computers, 2016)

Symbiotic system models for efficient IGT system design and test. - Cheng-Wen Wu; Bing-Yang Lin; Hsin-Wei Hung; Shu-Mei Tseng; Chi Chen (ITC-Asia, 2017)

Highly reliable and low-cost symbiotic IOT devices and systems. - Bing-Yang Lin; Hsin-Wei Hung; Shu-Mei Tseng; Chi Chen; Cheng-Wen Wu (ITC, 2017)

Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache. - Zhi-Yong Liu; Hsiu-Chuan Shih; Bing-Yang Lin; Cheng-Wen Wu (IEEE Des. Test, 2017)

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. - Kai-Li Wang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2017)

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. - Hsuan-Hung Liu; Bing-Yang Lin; Cheng-Wen Wu; Wan-Ting Chiang; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Trans. Computers, 2017)

Robustness of the Tangle 2.0 Consensus. - Bing-Yang Lin; Daria Dziubaltowska; Piotr Macek; Andreas Penzkofer; Sebastian Müller 006 (VALUETOOLS, 2022)

TangleSim: An Agent-based, Modular Simulator for DAG-based Distributed Ledger Technologies. - Bing-Yang Lin; Daria Dziubaltowska; Piotr Macek; Andreas Penzkofer; Sebastian Müller 006 (ICBC, 2023)

Evaluating Blockchain Consensus Mechanisms: A Comprehensive Three-Tiered Approach with Application to IOTA 2.0. - Bing-Yang Lin; Sebastian Müller 006; Luigi Vigneri; Ching-Hua Lin (BLOCKCHAIN, 2024)