An efficient and low power architecture design for motion estimation using global elimination algorithm. - Yu-Wen Huang; Shao-Yi Chien; Bing-Yu Hsieh; Liang-Gee Chen (ICASSP, 2002)

Simple and effective algorithm for automatic tracking of a single object using a pan-tilt-zoom camera. - Yu-Wen Huang; Bing-Yu Hsieh; Shao-Yi Chien; Liang-Gee Chen (ICME (1), 2002)

Automatic threshold decision of background registration technique for video segmentation. - Yu-Wen Huang; Shao-Yi Chien; Bing-Yu Hsieh; Liang-Gee Chen (VCIP, 2002)

Analysis and reduction of reference frames for motion estimation in MPEG-4 AVC/JVT/H.264. - Yu-Wen Huang; Bing-Yu Hsieh; Tu-Chih Wang; Shao-Yi Chien; Shyh-Yih Ma; Chun-Fu Shen; Liang-Gee Chen (ICASSP (3), 2003)

Architecture design for deblocking filter in H.264/JVT/AVC. - Yu-Wen Huang; To-Wei Chen; Bing-Yu Hsieh; Tu-Chih Wang; Te-Hao Chang; Liang-Gee Chen (ICME, 2003)

Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264. - Yu-Wen Huang; Tu-Chih Wang; Bing-Yu Hsieh; Liang-Gee Chen (ISCAS (2), 2003)

Fast motion estimation algorithm for H.264/MPEG-4 AVC by using multiple reference frame skipping criteria. - Bing-Yu Hsieh; Yu-Wen Huang; Tu-Chih Wang; Shao-Yi Chien; Liang-Gee Chen (VCIP, 2003)

Hardware architecture design for H.264/AVC intra frame coder. - Yu-Wen Huang; Bing-Yu Hsieh; Tung-Chien Chen; Liang-Gee Chen (ISCAS (2), 2004)

Global elimination algorithm and architecture design for fast block matching motion estimation. - Yu-Wen Huang; Shao-Yi Chien; Bing-Yu Hsieh; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2004)

Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques. - Shao-Yi Chien; Yu-Wen Huang; Bing-Yu Hsieh; Shyh-Yih Ma; Liang-Gee Chen (IEEE Trans. Multim., 2004)

Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder. - Yu-Wen Huang; Bing-Yu Hsieh; Tung-Chien Chen; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2005)

A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications. - Jyh-Shin Pan; Hao-Cheng Chen; Bing-Yu Hsieh; Hong-Ching Chen; Roger Lee; Ching-Ho Chu; Yuan-Chin Liu; Chuan Liu; Lily Huang; Chang-Long Wu; Meng-Hsueh Lin; Chun-Yiu Lin; et al. (DAC, 2006)

Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHY. - Jyh-Shin Pan; Tse-Hsiang Hsu; Hao-Cheng Chen; Jong-Woei Chen; Bing-Yu Hsieh; Hong-Ching Chen; Wei-Hsuan Tu; Chi-Ming Chang; Roger Lee; Ching-Ho Chu; Yuan-Chin Liu; Chuan-Cheng Hsiao; et al. (ISSCC, 2006)

Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC. - Tung-Chien Chen; Yu-Wen Huang; Chuan-Yung Tsai; Bing-Yu Hsieh; Liang-Gee Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC. - Yu-Wen Huang; Bing-Yu Hsieh; Shao-Yi Chien; Shyh-Yih Ma; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2006)

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems. - Shao-Yi Chien; Bing-Yu Hsieh; Yu-Wen Huang; Shyh-Yih Ma; Liang-Gee Chen (J. VLSI Signal Process., 2006)

An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. - Ping-Ying Wang; Jing-Hong Conan Zhan; Hsiang-Hui Chang; Bing-Yu Hsieh (CICC, 2008)

A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. - Hsiang-Hui Chang; Ping-Ying Wang; Jing-Hong Conan Zhan; Bing-Yu Hsieh (ISSCC, 2008)