Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. - Yajun Ha; Bingfeng Mei; Patrick Schaumont; Serge Vernalde; Rudy Lauwereins; Hugo De Man (FPL, 2001)

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (FPT, 2002)

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (DATE, 2003)

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (FPL, 2003)

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Rudy Lauwereins (DATE, 2004)

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. - Steven J. E. Wilton; Noha Kafafi; Bingfeng Mei; Serge Vernalde (FPT, 2004)

Design Style Case Study for Embedded Multi Media Compute Nodes. - Andy Lambrechts; Tom Vander Aa; Murali Jayapala; Guillermo Talavera; Anthony Leroy; Adelina Shickova; Francisco Barat; Bingfeng Mei; Francky Catthoor; Diederik Verkest; Geert Deconinck; Henk Corporaal; et al. (RTSS, 2004)

Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. - Bingfeng Mei; Francisco-Javier Veredas; Bart Masschelein (FPL, 2005)

Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. - Francisco-Javier Veredas; Michael Scheppler; Will Moffat; Bingfeng Mei (FPL, 2005)

Architecture Exploration for a Reconfigurable Architecture Template. - Bingfeng Mei; Andy Lambrechts; Diederik Verkest; Jean-Yves Mignolet; Rudy Lauwereins (IEEE Des. Test Comput., 2005)

Hardware and a Tool Chain for ADRES. - Bjorn De Sutter; Bingfeng Mei; T. Andrei Bartic; Tom Vander Aa; Mladen Berekovic; Jean-Yves Mignolet; Kris Croes; Paul Coene; Miro Cupac; Aïssa Couvreur; Andy Folens; Steven Dupont; et al. (ARC, 2006)

A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. - Tom Vander Aa; Bingfeng Mei; Bjorn De Sutter (CASES, 2007)

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays. - Bjorn De Sutter; Paul Coene; Tom Vander Aa; Bingfeng Mei (LCTES, 2008)

Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. - Bingfeng Mei; Bjorn De Sutter; Tom Vander Aa; M. Wouters; Andreas Kanstein; Steven Dupont (J. Signal Process. Syst., 2008)

Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor. - Mladen Berekovic; Andreas Kanstein; Bingfeng Mei; Bjorn De Sutter (Microprocess. Microsystems, 2009)

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures. - Andy Lambrechts; Praveen Raghavan; Murali Jayapala; Bingfeng Mei; Francky Catthoor; Diederik Verkest (IEEE Trans. Very Large Scale Integr. Syst., 2009)

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors. - Bjorn De Sutter; Osman Allam; Praveen Raghavan; Roeland Vandebriel; Hans Cappelle; Tom Vander Aa; Bingfeng Mei (J. Signal Process. Syst., 2010)