A universal state-of-charge algorithm for batteries. - Bingjun Xiao; Yiyu Shi 001; Lei He 001 (DAC, 2010)

Domain-specific processor with 3D integration for medical image processing. - Jason Cong; Karthik Gururaj; Muhuan Huang; Sen Li; Bingjun Xiao; Yi Zou (ASAP, 2011)

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration. - Jason Cong; Bingjun Xiao (NANOARCH, 2011)

FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). - Jason Cong; Bingjun Xiao (FPGA, 2012)

Optimizing routability in large-scale mixed-size placement. - Jason Cong; Guojie Luo; Kalliopi Tsota; Bingjun Xiao (ASP-DAC, 2013)

Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance. - Jason Cong; Bingjun Xiao (DAC, 2013)

Defect recovery in nanodevice-based programmable interconnects (abstract only). - Jason Cong; Bingjun Xiao (FPGA, 2013)

Optimization of interconnects between accelerators and shared memories in dark silicon. - Jason Cong; Bingjun Xiao (ICCAD, 2013)

Accelerator-rich CMPs: From concept to real hardware. - Yu-Ting Chen 003; Jason Cong; Mohammad Ali Ghodrat; Muhuan Huang; Chunyue Liu; Bingjun Xiao; Yi Zou (ICCD, 2013)

Energy-efficient computing using adaptive table lookup based on nonvolatile memories. - Jason Cong; Milos D. Ercegovac; Muhuan Huang; Sen Li; Bingjun Xiao (ISLPED, 2013)

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. - Jason Cong; Peng Li 031; Bingjun Xiao; Peng Zhang 007 (DAC, 2014)

A Fully Pipelined and Dynamically Composable Architecture of CGRA. - Jason Cong; Hui Huang 001; Chiyuan Ma; Bingjun Xiao; Peipei Zhou 001 (FCCM, 2014)

Minimizing Computation in Convolutional Neural Networks. - Jason Cong; Bingjun Xiao (ICANN, 2014)

FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. - Jason Cong; Bingjun Xiao (IEEE Trans. Very Large Scale Integr. Syst., 2014)

CMOST: a system-level FPGA compilation framework. - Peng Zhang 007; Muhuan Huang; Bingjun Xiao; Hui Huang 001; Jason Cong (DAC, 2015)

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. - Chen Zhang 001; Peng Li 031; Guangyu Sun 003; Yijin Guan; Bingjun Xiao; Jason Cong (FPGA, 2015)

ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures. - Yu-Ting Chen 003; Jason Cong; Bingjun Xiao (ISPASS, 2015)

Communication Optimization for Customizable Domain-Specific Computing. - Bingjun Xiao (2015)

Customizable Computing - Yu-Ting Chen 003; Jason Cong; Michael Gill; Glenn Reinman; Bingjun Xiao (Morgan & Claypool Publishers, 2015)

Novel applications of deep learning hidden features for adaptive testing. - Bingjun Xiao; Jinjun Xiong; Yiyu Shi 001 (ASP-DAC, 2016)

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures. - Yu-Ting Chen 003; Jason Cong; Zhenman Fang; Bingjun Xiao; Peipei Zhou 001 (CoRR, 2016)

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers. - Jason Cong; Peng Li 031; Bingjun Xiao; Peng Zhang 007 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)