Performance modelling of heterogeneous ISA multicore architectures. - Nirmal Kumar Boran; Rameshwar Prasad Meghwal; Kuldeep Sharma; Binod Kumar 001; Virendra Singh (EWDTS, 2016)

A trace signal selection algorithm for improved post-silicon debug. - Binod Kumar 001; Ankit Jindal; Virendra Singh (EWDTS, 2016)

A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. - Binod Kumar 001; Boda Nehru; Brajesh Pandey; Virendra Singh; Jaynarayan T. Tudu (EWDTS, 2016)

Skip-scan: A methodology for test time reduction. - Binod Kumar 001; Boda Nehru; Brajesh Pandey; Jaynarayan T. Tudu (VDAT, 2016)

Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. - Binod Kumar 001; Ankit Jindal; Masahiro Fujita; Virendra Singh (ACM Great Lakes Symposium on VLSI, 2017)

RTL level trace signal selection and coverage estimation during post-silicon validation. - Binod Kumar 001; Kanad Basu; Masahiro Fujita; Virendra Singh (HLDVT, 2017)

Revisiting random access scan for effective enhancement of post-silicon observability. - Binod Kumar 001; Ankit Jindal; Jaynarayan T. Tudu; Brajesh Pandey; Virendra Singh (IOLTS, 2017)

Post-silicon observability enhancement with topology based trace signal selection. - Binod Kumar 001; Ankit Jindal; Masahiro Fujita; Virendra Singh (LATS, 2017)

Testing multiple stuck-at faults of ROBDD based combinational circuit design. - Toral Shah; Anzhela Yu. Matrosova; Binod Kumar 001; Masahiro Fujita; Virendra Singh (LATS, 2017)

A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. - Binod Kumar 001; Kanad Basu; Ankit Jindal; Brajesh Pandey; Masahiro Fujita (VDAT, 2017)

Improving post-silicon error detection with topological selection of trace signals. - Binod Kumar 001; Kanad Basu; Ankit Jindal; Masahiro Fujita; Virendra Singh (VLSI-SoC, 2017)

A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. - Binod Kumar 001; Ankit Jindal; Virendra Singh; Masahiro Fujita (VLSID, 2017)

A Novel Shared Active Pixel Architecture (SAPA) with Low Dark Current and High Fill-Factor (FF) for CMOS Image Sensors. - Vinay Kumar; Krishna Lal Baishnab; Binod Kumar 001 (J. Low Power Electron., 2017)

A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. - Binod Kumar 001; Kanad Basu; Virendra Singh (IGSC, 2018)

Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. - Ankit Jindal; Binod Kumar 001; Nitish Jindal; Masahiro Fujita; Virendra Singh (ISVLSI, 2018)

ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. - Ankit Jindal; Binod Kumar 001; Kanad Basu; Masahiro Fujita (VLSID, 2018)

Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. - Binod Kumar 001; Atul Kumar Bhosale; Masahiro Fujita; Virendra Singh (ATS, 2019)

Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. - Vineesh V. S.; Binod Kumar 001; Rushikesh Shinde; Akshay Jaiswal; Harsh Bhargava; Virendra Singh (ATS, 2019)

A Unified Methodology for Hardware Obfuscation and IP Watermarking. - Saurabh Gangurde; Binod Kumar 001 (VDAT, 2019)

Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods. - V. S. Vineesh; Binod Kumar 001; Jay Adhaduk (VDAT, 2019)

A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. - Binod Kumar 001; Masahiro Fujita; Virendra Singh (VLSID, 2019)

SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. - Binod Kumar 001; Masahiro Fujita; Virendra Singh (J. Electron. Test., 2019)

Power-Delay-Error-Efficient Approximate Adder for Error-Resilient Applications. - Vinay Kumar; Ankit Singh; Shubham Upadhyay; Binod Kumar 001 (J. Circuits Syst. Comput., 2019)

Analyzing Hardware Security Properties of Processors through Model Checking. - Binod Kumar 001; Akshay Kumar Jaiswal; V. S. Vineesh; Rushikesh Shinde (VLSID, 2020)

A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. - Binod Kumar 001; Swapniel Thakur; Kanad Basu; Masahiro Fujita; Virendra Singh (VLSID, 2020)

DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs. - Nandan Kumar Jha; Sparsh Mittal; Binod Kumar 001; Govardhan Mattela (ACM J. Emerg. Technol. Comput. Syst., 2020)

Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. - Binod Kumar 001; Kanad Basu; Masahiro Fujita; Virendra Singh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. - Binod Kumar 001; Jay Adhaduk; Kanad Basu; Masahiro Fujita; Virendra Singh (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Enhancing Testbench Quality via Genetic Algorithm. - Harsh Bhargav; Vineesh V. S.; Binod Kumar 001; Virendra Singh (MWSCAS, 2021)

Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. - V. S. Vineesh; Binod Kumar 001; Rushikesh Shinde; Neelam Sharma; Masahiro Fujita; Virendra Singh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test. - Utsav Jana; Sourav Banerjee; Binod Kumar 001; Madhu B; Shankar Umapathi; Masahiro Fujita (ATS, 2022)

Blood Pressure Estimation from ECG Data Using XGBoost and ANN for Wearable Devices. - Sourav Banerjee; Binod Kumar 001; Alex Pappachen James; Jai Narayan Tripathi (ICECS 2022, 2022)

Hardware Accelerator Design for Healthcare Applications: Review and Perspectives. - Jai Narayan Tripathi; Binod Kumar 001; Dinesh Junjariya (ISCAS, 2022)

Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. - Binod Kumar 001; V. S. Vineesh; Puneet Nemade; Masahiro Fujita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Case Study on Formally Verifying an Open-source Deep Learning Accelerator Design. - Anshul Jain; Binod Kumar 001 (ATS, 2023)

LLM-aided Front-End Design Framework For Early Development of Verified RTLs. - Vyom Kumar Gupta; Abhishek Yadav; Masahiro Fujita; Binod Kumar 001 (ATS, 2024)

MEMFD: A Multi-EDT Multi-Fault Scan Chain Diagnosis Methodology with Deep Learning. - Saman Aijaz Siddiqui; Uzair Ruhulamin Patel; Utsav Jana; Binod Kumar 001 (ATS, 2024)

A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Network Implementation. - Abhishek Yadav; Ayush Dixit; Utsav Jana; Binod Kumar 001 (iSES, 2024)

Harnessing Knowledge-Distillation for Lightweight AI-Implementation on Resource-Constrained Device. - Abhishek Yadav; Vyom Kumar Gupta; Binod Kumar 001 (iSES, 2024)

Resource-efficient DL Model Inference with Weight Clustering and Zero-skipping. - Abhishek Yadav; Masahiro Fujita; Binod Kumar 001 (ISOCC, 2024)

Lightweight DL-based Drone Image Classification for Surveillance Applications. - Abhishek Yadav; Masahiro Fujita; Binod Kumar 001 (ISOCC, 2024)

Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance Applications. - Abhishek Yadav; Vyom Kumar Gupta; Kethireddy Harshith Reddy; Masahiro Fujita; Binod Kumar 001 (VLSID, 2025)

On-Chip Implementation of Neural Network-Based Classifier Models for E-Nose With Chemometric Analysis. - Vyom Kumar Gupta; Abhishek Yadav; Mirgender Kumar; Binod Kumar 001; Sunny (IEEE Trans. Instrum. Meas., 2025)