Robust ultra-low power sub-threshold DTMOS logic. - Hendrawan Soeleman; Kaushik Roy 001; Bipul Chandra Paul (ISLPED, 2000)

Design Verification and Robust Design Technique for Cross-Talk Faults. - Bipul Chandra Paul; Seung Hoon Choi; Yonghee Im; Kaushik Roy 001 (Asian Test Symposium, 2001)

Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. - Hendrawan Soeleman; Kaushik Roy 001; Bipul Chandra Paul (VLSI Design, 2001)

Robust subthreshold logic for ultra-low power operation. - Hendrawan Soeleman; Kaushik Roy 001; Bipul Chandra Paul (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. - Bipul Chandra Paul; Kaushik Roy 001 (ITC, 2002)

Dynamic Noise Analysis with Capacitive and Inductive Coupling. - Seung Hoon Choi; Bipul Chandra Paul; Kaushik Roy 001 (ASP-DAC/VLSI Design, 2002)

Adaptive supply voltage technique for low swing interconnects. - Woopyo Jeong; Bipul Chandra Paul; Kaushik Roy 001 (ASP-DAC, 2004)

Process variation in nano-scale memories: failure analysis and process tolerant architecture. - Amit Agarwal 001; Bipul C. Paul; Kaushik Roy 001 (CICC, 2004)

Novel sizing algorithm for yield improvement under process variation in nanometer technology. - Seung Hoon Choi; Bipul Chandra Paul; Kaushik Roy 001 (DAC, 2004)

A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. - Amit Agarwal 001; Bipul Chandra Paul; Kaushik Roy 001 (IOLTS, 2004)

Device optimization for ultra-low power digital sub-threshold operation. - Bipul Chandra Paul; Arijit Raychowdhury; Kaushik Roy 001 (ISLPED, 2004)

Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. - Bipul Chandra Paul; Cassondra Neau; Kaushik Roy 001 (ITC, 2004)

Enhancing Yield at the End of the Technology Roadmap. - Naran Sirisantana; Bipul Chandra Paul; Kaushik Roy 001 (IEEE Des. Test Comput., 2004)

Statistical Timing Analysis using Levelized Covariance Propagation. - Kunhyuk Kang; Bipul Chandra Paul; Kaushik Roy 001 (DATE, 2005)

Process variation in embedded memories: failure analysis and variation aware architecture. - Amit Agarwal 001; Bipul C. Paul; Saibal Mukhopadhyay; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2005)

A process-tolerant cache architecture for improved yield in nanoscale technologies. - Amit Agarwal 001; Bipul Chandra Paul; Hamid Mahmoodi-Meimand; Animesh Datta; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. - Arijit Raychowdhury; Bipul Chandra Paul; Swarup Bhunia; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Modeling and analysis of circuit performance of ballistic CNFET. - Bipul C. Paul; Shinobu Fujita; Masaki Okajima; Thomas Lee (DAC, 2006)

Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. - Bipul Chandra Paul; Kunhyuk Kang; Haldun Kufluoglu; Muhammad Ashraful Alam; Kaushik Roy 001 (DATE, 2006)

Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. - Arijit Raychowdhury; Bipul Chandra Paul; Swarup Bhunia; Kaushik Roy 001 (DATE, 2006)

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. - Bipul C. Paul; Kaushik Roy 001 (J. Electron. Test., 2006)

Low-power design techniques for scaled technologies. - Bipul Chandra Paul; Amit Agarwal 001; Kaushik Roy 001 (Integr., 2006)

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. - Aditya Bansal; Bipul Chandra Paul; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. - Kunhyuk Kang; Bipul C. Paul; Kaushik Roy 001 (ACM Trans. Design Autom. Electr. Syst., 2006)

Circuit Failure Prediction and Its Application to Transistor Aging. - Mridul Agarwal; Bipul C. Paul; Ming Zhang; Subhasish Mitra (VTS, 2007)

Prospect of ballistic CNFET in high performance applications: Modeling and analysis. - Bipul C. Paul; Shinobu Fujita; Masaki Okajima; Thomas Lee (ACM J. Emerg. Technol. Comput. Syst., 2007)

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. - Bipul Chandra Paul; Kunhyuk Kang; Haldun Kufluoglu; Muhammad Ashraful Alam; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

ROM based logic (RBL) design: High-performance and low-power adders. - Bipul Chandra Paul; Shinobu Fujita; Masaki Okajima (ISCAS, 2008)

Optimized Circuit Failure Prediction for Aging: Practicality and Promise. - Mridul Agarwal; Varsha Balakrishnan; Anshuman Bhuyan; Kyunglok Kim; Bipul C. Paul; Wenping Wang 004; Bo Yang; Yu Cao 001; Subhasish Mitra (ITC, 2008)

Advances in nanoelectronics circuits and systems [Editorial]. - Bipul C. Paul; Krishnendu Chakrabarty (IET Comput. Digit. Tech., 2009)

ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier. - Bipul C. Paul; Shinobu Fujita; Masaki Okajima (IEEE J. Solid State Circuits, 2009)

Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. - Bipul C. Paul; Arijit Raychowdhury (Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011)

Introduction to the special issue on memory technologies. - Bipul C. Paul; Arijit Raychowdhury (ACM J. Emerg. Technol. Comput. Syst., 2013)

A Retrospective View on the Technology Evolution to Support Low Power Mobile Application. - Bipul C. Paul; Ajey P. Jacob; William Taylor; Randy W. Mann; Joseph Versaggi; Edward J. Nowak; Lars W. Liebmann (J. Low Power Electron., 2018)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Physics based MTJ Compact Model for State-of-the-Art and Emerging STT-MRAM Failure Analysis and Yield Enhancement. - Nishtha S. Gaul; Akhilesh Jaiswal 002; Hongsik Yoon; Taeyoung Lee; Kazutaka Yamane; Joseph Versaggi; Rick Carter; Bipul C. Paul (IMW, 2022)