A self-powered wireless bolt for smart critical fastener. - Biruk B. Seyoum; Maurizio Rossi 001; Davide Brunelli (GIoTS, 2017)

Energy Neutral Wireless Bolt for Safety Critical Fastening. - Biruk B. Seyoum; Maurizio Rossi 001; Davide Brunelli (Sensors, 2017)

FLORA: FLoorplan Optimizer for Reconfigurable Areas in FPGAs. - Biruk B. Seyoum; Alessandro Biondi 001; Giorgio C. Buttazzo (ACM Trans. Embed. Comput. Syst., 2019)

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC. - Biruk B. Seyoum; Marco Pagani; Alessandro Biondi 001; Giorgio C. Buttazzo (SAC, 2021)

Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs. - Biruk B. Seyoum; Marco Pagani; Alessandro Biondi 001; Sara Balleri; Giorgio C. Buttazzo (IEEE Trans. Computers, 2021)

Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs. - Biruk B. Seyoum; Davide Giri; Kuan-Lin Chiu; Luca P. Carloni (CASES, 2022)

EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators. - Kuan-Lin Chiu; Guy Eichler; Biruk B. Seyoum; Luca P. Carloni (CPS-IoT Week Workshops, 2023)

PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs. - Biruk B. Seyoum; Davide Giri; Kuan-Lin Chiu; Bryce Natter; Luca P. Carloni (DATE, 2023)

MindCrypt: The Brain as a Random Number Generator for SoC-Based Brain-Computer Interfaces. - Guy Eichler; Biruk B. Seyoum; Kuan-Lin Chiu; Luca P. Carloni (ICCD, 2023)