Building supply chain communication systems: a review of methods and techniques. - Anne-Françoise Cutting-Decelle; Bishnu Prasad Das; Robert I. M. Young; Keith Case; Shahin Rahimifard; Chimay J. Anumba; N. M. Bouchlaghem (Data Sci. J., 2006)

Towards the understanding of the requirements of a communication language to support process interoperation in cross-disciplinary supply chains. - Bishnu Prasad Das; Anne-Françoise Cutting-Decelle; Robert I. M. Young; Keith Case; Shahin Rahimifard; Chimay J. Anumba; N. M. Bouchlaghem (Int. J. Comput. Integr. Manuf., 2007)

A review of approaches to supply chain communications: from manufacturing to construction. - Anne-Françoise Cutting-Decelle; Bob Young; Bishnu Prasad Das; Keith Case; Shahin Rahimifard; Chimay J. Anumba; Dino Bouchlaghem (J. Inf. Technol. Constr., 2007)

Within-die gate delay variability measurement using re-configurable ring oscillator. - Bishnu Prasad Das; Bharadwaj Amrutur; H. S. Jamadagni; N. V. Arvind; V. Visvanathan (CICC, 2008)

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. - Bishnu Prasad Das; Janakiraman Viraraghavan; Bharadwaj Amrutur; H. S. Jamadagni; N. V. Arvind (VLSI Design, 2008)

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. - Janakiraman Viraraghavan; Bishnu Prasad Das; Bharadwaj Amrutur (VLSI Design, 2008)

Warning Prediction Sequential for Transient Error Prevention. - Bishnu Prasad Das; Hidetoshi Onodera (DFT, 2010)

Learning Collaboration Moderator Services: Supporting Knowledge Based Collaboration. - Alok Kumar Choudhary; Jenny A. Harding; Rahul Swarnkar; Bishnu Prasad Das; Robert I. M. Young (PRO-VE, 2010)

Application of Collaboration Moderator Service in Pharmaceutical Industry: A Collaborative Drug Discovery Use Case. - Rahul Swarnkar; Jennifer A. Harding; Bishnu Prasad Das; Robert I. M. Young; Sri Krishna Kumar (I-ESA, 2012)

Area-efficient reconfigurable-array-based oscillator for standard cell characterisation. - Bishnu Prasad Das; Hidetoshi Onodera (IET Circuits Devices Syst., 2012)

A framework for collaboration moderator services to support knowledge based collaboration. - Rahul Swarnkar; Alok Kumar Choudhary; Jenny A. Harding; Bishnu Prasad Das; Robert I. M. Young (J. Intell. Manuf., 2012)

Generating rules from data mining for collaboration moderator services. - Claire Palmer; Jennifer A. Harding; Rahul Swarnkar; Bishnu Prasad Das; Robert I. M. Young (J. Intell. Manuf., 2013)

Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack. - Kaushik Vaidyanathan; Bishnu Prasad Das; Larry T. Pileggi (DAC, 2014)

Building trusted ICs using split fabrication. - Kaushik Vaidyanathan; Bishnu Prasad Das; Huseyin Ekin Sumbul; Renzhi Liu; Larry T. Pileggi (HOST, 2014)

On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator. - Bishnu Prasad Das; Hidetoshi Onodera (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs. - Bishnu Prasad Das; Hidetoshi Onodera (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance. - Govinda Sannena; Bishnu Prasad Das (ACM Great Lakes Symposium on VLSI, 2016)

Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application. - Govinda Sannena; Bishnu Prasad Das (iNIS, 2016)

A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications. - Swaati; Bishnu Prasad Das (VDAT, 2017)

Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator. - Poorvi Jain; Bishnu Prasad Das (VLSID, 2017)

Metastability immune and area efficient error masking flip-flop for timing error resilient designs. - Govinda Sannena; Bishnu Prasad Das (Integr., 2018)

Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring. - Govinda Sannena; Bishnu Prasad Das (IEEE Trans. Very Large Scale Integr. Syst., 2018)

An In-Memory Architecture for Machine Learning Classifier Using Logistic Regression. - Prasanna Kumar Saragada; Meghnath Rathod; Bishnu Prasad Das (iSES, 2019)

Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series. - Sumit Satyavijay Wadkar; Bishnu Prasad Das; Pramod Kumar Meher (iSES, 2019)

A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs. - Priyamvada Sharma; Bishnu Prasad Das (VDAT, 2019)

An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications. - Priyamvada Sharma; Poorvi Jain; Bishnu Prasad Das (Microelectron. J., 2019)

RISC-V Core with Approximate Multiplier for Error-Tolerant Applications. - Anu Verma; Priyamvada Sharma; Bishnu Prasad Das (DSD, 2022)

Highly Non-linear Feed-Forward Arbiter PUF Against Machine Learning Attacks. - Aranya Gupta; Sanjeev Manhas; Bishnu Prasad Das (VDAT, 2022)

Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications. - Anshul Verma; Bishnu Prasad Das (VDAT, 2022)

In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code. - Prasanna Kumar Saragada; Bishnu Prasad Das (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Area-Efficient In-Memory Computation with Improved Linearity using Voltage-Controlled Delay Cell-based Ring Oscillator. - Amandeep Singh; Bishnu Prasad Das (iSES, 2023)

Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient Application. - Apurba Prasad Padhy; Bishnu Prasad Das (VLSID, 2023)

Ultra-Low Power Non-Uniform SAR ADC based ECG detector for Early Detection of Cardiovascular Diseases. - Aditya Ramkumar; Anshul Verma; Bishnu Prasad Das (VLSID, 2023)

An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation. - Anu Verma; Khyati Kiyawat; Bishnu Prasad Das; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2023)

PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks. - Amandeep Singh; Bishnu Prasad Das (ISCAS, 2024)

A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases. - Sidharth Thomas; Jaskirat Singh Virdi; Anshul Verma; Bishnu Prasad Das; Kenichi Okada 001; Pratap Narayan Singh (ISCAS, 2024)

A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter. - Anshul Verma; Bishnu Prasad Das (VLSID, 2024)

Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC. - Prasanna Kumar Saragada; Bishnu Prasad Das (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)