An Efficient Methodology for Full Chip Signal ElectroMigration Analysis for Advanced Technology Node Designs. - Biswajit Patra; Nayan Chandak; Amlan Chakrabarti (J. Low Power Electron., 2011)

A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes. - Biswajit Patra; Sanatan Chattopadhyay; Amlan Chakrabarti (VDAT, 2012)

Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes. - Biswajit Patra; Amlan Chakrabarti; Sanatan Chattopadhyay (J. Low Power Electron., 2014)

A framework for energy efficient and flexible offloading scheme for handheld devices. - Biswajit Patra; Sarbani Roy; Chandreyee Chowdhury (IEEE ANTS, 2015)

Usability, tested? - Neha Kumar 001; Naveena Karusala; Aaditeshwar Seth; Biswajit Patra (Interactions, 2017)

8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package. - Wilfred Gomes; Sanjeev Khushu; Doug B. Ingerly; Patrick N. Stover; Nasirul I. Chowdhury; Frank O'Mahony; Ajay Balankutty; Noam Dolev; Martin G. Dixon; Lei Jiang; Surya Prekke; Biswajit Patra; et al. (ISSCC, 2020)

Precise and Faster Image Description Generation with Limited Resources Using an Improved Hybrid Deep Model. - Biswajit Patra; Dakshina Ranjan Kisku (PReMI, 2023)

Does digital payment induce economic growth in emerging economies? The mediating role of institutional quality, consumption expenditure, and bank credit. - Biswajit Patra; Narayan Sethi (Inf. Technol. Dev., 2024)

Modeling International Tourist Arrivals: An NLP Perspective. - Archana Yadav; Biswajit Patra; Tanmay Basu (Oper. Res. Forum, 2024)