Winograd-Based Real-Time Super-Resolution System on FPGA. - Bizhao Shi; Zhucheng Tang; Guojie Luo; Ming Jiang 001 (FPT, 2019)

BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. - Zhe Zhou 002; Bizhao Shi; Zhe Zhang 006; Yijin Guan; Guangyu Sun 003; Guojie Luo (DAC, 2021)

EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper). - Jiaxi Zhang 001; Qiuyang Gao; Yijiang Guo; Bizhao Shi; Guojie Luo (ASP-DAC, 2022)

2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration. - Sicheng Li 001; Chen Bai; Xuechao Wei; Bizhao Shi; Yen-Kuang Chen; Yuan Xie 001 (ICCAD, 2022)

Weave: Abstraction for Accelerator Integration of Generated Modules. - Tuo Dai; Bizhao Shi; Guojie Luo (FPGA, 2023)

F-TFM: Accelerating Total Focusing Method for Ultrasonic Array Imaging on FPGA. - Bizhao Shi; Jieran Zhang; Guojie Luo (ICFPT, 2023)

RF-SIFTER: Sifting Signals at Layer-0.5 to Mitigate Wideband Cross-Technology Interference for IoT. - Xiong Wang 006; Jun Huang 001; Bizhao Shi; Zhe Ou; Guojie Luo; Linghe Kong; Daqing Zhang 001; Chenren Xu (MobiCom, 2023)

Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. - Bizhao Shi; Jiaxi Zhang 001; Zhuolun He; Xuechao Wei; Sicheng Li 001; Guojie Luo; Hongzhong Zheng; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning. - Tuo Dai; Bizhao Shi; Guojie Luo (DAC, 2024)

PT-Map: Efficient Program Transformation Optimization for CGRA Mapping. - Bizhao Shi; Tuo Dai; Jiaxi Zhang 001; Xuechao Wei; Guojie Luo (DAC, 2024)

WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on ACAP. - Tuo Dai; Bizhao Shi; Guojie Luo (DATE, 2024)

BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call. - Sunan Zou; Jiaxi Zhang 001; Bizhao Shi; Guojie Luo (DATE, 2024)

ImageMap: Enabling Efficient Mapping from Image Processing DSL to CGRA. - Bizhao Shi; Tuo Dai; Sunan Zou; Xinming Wei; Guojie Luo (Euro-Par (1), 2024)

MuSA: Multi-Sketch Accelerator with Hybrid Parallelism and Coalesced Memory Organization. - Sunan Zou; Bizhao Shi; Ziyun Zhang; Guojie Luo (ICCD, 2024)

WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on the Versal ACAP Architecture. - Tuo Dai; Bizhao Shi; Guojie Luo (CoRR, 2024)

PowerSyn: A Logic Synthesis Framework With Early Power Optimization. - Sunan Zou; Jiaxi Zhang 001; Bizhao Shi; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Weave: Abstraction and Integration Flow for Accelerators of Generated Modules. - Tuo Dai; Bizhao Shi; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

TACPlace: Ultrafast Thermal-Aware Chiplet Placement with Feasibility Seeking. - Shan Yu; Haiyang Liu; Xinming Wei; Bizhao Shi; Guojie Luo (ACM Great Lakes Symposium on VLSI, 2025)