A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applications. - Thomas E. Bonnerud; Bjørnar Hernes; Trond Ytterdal (CICC, 2001)

A -80 dB HD3 opamp in 3.3 V CMOS technology using tail current compensation. - Bjørnar Hernes; Øystein Moldsvor; Trond Sæther (ISCAS (1), 2001)

A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS. - Terje N. Andersen; Atle Briskemyr; Frode Telstø; Johnny Bjørnsen; Thomas E. Bonnerud; Bjørnar Hernes; Øystein Moldsvor (DATE, 2004)

A 97mW 110MS/s 12b pipeline ADC implemented in 0.18μm digital CMOS. - Terje N. Andersen; Atle Briskemyr; Frode Telstø; Johnny Bjørnsen; Thomas E. Bonnerud; Bjørnar Hernes; Øystein Moldsvor (ESSCIRC, 2004)

A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS. - Terje Nortvedt Andersen; Bjørnar Hernes; Atle Briskemyr; Frode Telstø; Johnny Bjørnsen; Thomas E. Bonnerud; Øystein Moldsvor (IEEE J. Solid State Circuits, 2005)

Distortion in single-, two- and three-stage amplifiers. - Bjørnar Hernes; Willy M. C. Sansen (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Quantizer Nonoverload Criteria in Sigma-Delta Modulators. - Ivar Løkken; Anders Vinje; Trond Sæther; Bjørnar Hernes (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS. - Bjørnar Hernes; Johnny Bjørnsen; Terje N. Andersen; Anders Vinje; Havard Korsvoll; Frode Telstø; Atle Briskemyr; Christian Holdo; Øystein Moldsvor (ISSCC, 2007)

A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOS. - Rune Kaald; Bjørnar Hernes; Christian Holdo; Frode Telstø; Ivar Løkken (CICC, 2013)