Designing an FPGA SoC Using a Standardized IP Block Interface. - Lesley Shannon; Blair Fort; Samir Parikh; Arun Patel; Manuel Saldaña; Paul Chow (FPT, 2005)

Experiences with Soft-Core Processor Design. - Franjo Plavec; Blair Fort; Zvonko G. Vranesic; Stephen Dean Brown (IPDPS, 2005)

A Multithreaded Soft Processor for SoPC Area Reduction. - Blair Fort; Davor Capalija; Zvonko G. Vranesic; Stephen Dean Brown (FCCM, 2006)

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. - Lesley Shannon; Blair Fort; Samir Parikh; Arun Patel; Manuel Saldaña; Paul Chow (FPL, 2006)

From software to accelerators with LegUp high-level synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Ruolong Lian; Qijing Huang 001; Nazanin Calagar; Marcel Gort; Jia Jun Qin; Mark Aldham; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (CASES, 2013)

From C to Blokus Duo with LegUp high-level synthesis. - Jiu Cheng Cai; Ruolong Lian; Mengyao Wang; Andrew Canis; Jongsok Choi; Blair Fort; Eric Hart; Emily Miao; Yanyan Zhang; Nazanin Calagar; Stephen Brown 003; Jason Helge Anderson (FPT, 2013)

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. - Blair Fort; Andrew Canis; Jongsok Choi; Nazanin Calagar; Ruolong Lian; Stefan Hadjis; Yu Ting Chen; Mathew Hall; Bain Syrowik; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (EUC, 2014)

LegUp High-Level Synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Bain Syrowik; Ruolong Lian; Yu Ting Chen; Hsuan Hsiao; Jeffrey B. Goeders; Stephen Brown 003; Jason Helge Anderson (FPGAs for Software Programmers, 2016)

A Survey and Evaluation of FPGA High-Level Synthesis Tools. - Razvan Nane; Vlad Mihai Sima; Christian Pilato; Jongsok Choi; Blair Fort; Andrew Canis; Yu Ting Chen; Hsuan Hsiao; Stephen Brown 003; Fabrizio Ferrandi; Jason Helge Anderson; Koen Bertels (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

FISH: Linux system calls for FPGA accelerators. - Kevin Nam; Blair Fort; Stephen Brown 003 (FPL, 2017)

Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. - Bain Syrowik; Blair Fort; Stephen Dean Brown (HEART, 2018)