Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs. - Edinei Santin; Luís B. Oliveira; Blazej Nowacki; João Goes (ISCAS, 2010)

A 1.2 V 300 μW second-order switched-capacitor Δ∑ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS. - Blazej Nowacki; Nuno Paulino 002; João Goes (ESSCIRC, 2011)

A second-order switched-capacitor ΔΣ modulator using very incomplete settling. - Blazej Nowacki; Nuno Paulino 002; João Goes (ISCAS, 2011)

A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters. - Edinei Santin; Luís B. Oliveira; Blazej Nowacki; João Goes (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Design methodology for Sigma-Delta modulators based on a genetic algorithm using hybrid cost functions. - João L. A. de Melo; Blazej Nowacki; Nuno Paulino 002; João Goes (ISCAS, 2012)

A simple 1 GHz non-overlapping two-phase clock generators for SC circuits. - Blazej Nowacki; Nuno Paulino 002; João Goes (MIXDES, 2013)

A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling. - Blazej Nowacki; Nuno Paulino 002; João Goes (ISCAS, 2014)

15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM. - Blazej Nowacki; Nuno Paulino 002; João Goes (ISSCC, 2016)

A Third-Order MASH $ Sigma Delta $ Modulator Using Passive Integrators. - Blazej Nowacki; Nuno Paulino 002; João Goes (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators. - Inês Nogueira De Brito; Nuno Paulino 002; Blazej Nowacki; Tommy Mullane (PRIME, 2023)