A Security Protocol for Biometric Smart Cards. - David Hwang 001; Bo-Cheng Lai; Patrick Schaumont; Ingrid Verbauwhede (CARDIS, 2002)

Leakage power analysis of a 90nm FPGA. - Tim Tuan; Bo-Cheng Lai (CICC, 2003)

Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. - David D. Hwang; Bo-Cheng Lai; Patrick Schaumont; Kazuo Sakiyama; Yi Fan; Shenglin Yang; Alireza Hodjat; Ingrid Verbauwhede (DAC, 2003)

Testing ThumbPod: Softcore bugs are hard to find. - Patrick Schaumont; Kazuo Sakiyama; Yi Fan; David D. Hwang; Shenglin Yang; Alireza Hodjat; Bo-Cheng Lai; Ingrid Verbauwhede (HLDVT, 2003)

Energy-Memory-Security Tradeoffs in Distributed Sensor Networks. - David Hwang 001; Bo-Cheng Lai; Ingrid Verbauwhede (ADHOC-NOW, 2004)

Reducing radio energy consumption of key management protocols for wireless sensor networks. - Bo-Cheng Lai; David Hwang 001; Sungha Pete Kim; Ingrid Verbauwhede (ISLPED, 2004)

Security for Ambient Intelligent Systems. - Ingrid Verbauwhede; Alireza Hodjat; David Hwang 001; Bo-Cheng Lai (Ambient Intelligence, 2005)

Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. - Kris Tiri; David D. Hwang; Alireza Hodjat; Bo-Cheng Lai; Shenglin Yang; Patrick Schaumont; Ingrid Verbauwhede (CHES, 2005)

Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. - Patrick Schaumont; Bo-Cheng Charles Lai; Wei Qin; Ingrid Verbauwhede (DAC, 2005)

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. - Kris Tiri; David D. Hwang; Alireza Hodjat; Bo-Cheng Lai; Shenglin Yang; Patrick Schaumont; Ingrid Verbauwhede (DAC, 2005)

A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. - Alireza Hodjat; David Hwang 001; Bo-Cheng Lai; Kris Tiri; Ingrid Verbauwhede (ACM Great Lakes Symposium on VLSI, 2005)

Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System. - Bo-Cheng Charles Lai; Patrick Schaumont; Wei Qin; Ingrid Verbauwhede (ICCD, 2005)

Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. - Bo-Cheng Charles Lai; Patrick Schaumont; Wei Qin; Ingrid Verbauwhede (ASAP, 2006)

AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. - David D. Hwang; Kris Tiri; Alireza Hodjat; Bo-Cheng Lai; Shenglin Yang; Patrick Schaumont; Ingrid Verbauwhede (IEEE J. Solid State Circuits, 2006)

A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems. - Jongsun Kim; Bo-Cheng Lai; Mau-Chung Frank Chang; Ingrid Verbauwhede (IEEE Trans. Computers, 2008)

Unleash the parallelism of 3DIC partitioning on GPGPU. - Hsien-Kai Kuo; Bo-Cheng Charles Lai; Jing-Yang Jou (SoCC, 2010)

Classifier Grouping to Enhance Data Locality for a Multi-threaded Object Detection Algorithm. - Bo-Cheng Charles Lai; Chih-Hsuan Chiang; Guan-Ru Li (ICPADS, 2011)

A highly parallel design for irregular LDPC decoding on GPGPUs. - Tsou-Han Chiu; Hsien-Kai Kuo; Bo-Cheng Charles Lai (APSIPA, 2012)

Thread affinity mapping for irregular data access on shared Cache GPGPU. - Hsien-Kai Kuo; Kuan-Ting Chen; Bo-Cheng Charles Lai; Jing-Yang Jou (ASP-DAC, 2012)

Reduce Data Coherence Cost with an Area Efficient Double Layer Counting Bloom Filter. - Kuan-Ting Chen; Ping-Ru Wu; Bo-Cheng Charles Lai (PAAP, 2012)

A highly parallel design of image surface layout recovering on GPGPU. - Guan-Ru Li; Bo-Cheng Charles Lai (VLSI-DAT, 2012)

Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. - Hsien-Kai Kuo; Ta-Kan Yen; Bo-Cheng Charles Lai; Jing-Yang Jou (ASP-DAC, 2013)

A Locality-Aware Dynamic Thread Scheduler for GPGPUs. - Yu-Hao Huang; Ying-Yu Tseng; Hsien-Kai Kuo; Ta-Kan Yen; Bo-Cheng Charles Lai (PDCAT, 2013)

Memory capacity aware non-blocking data transfer on GPGPU. - Hao-Wei Liu; Hsien-Kai Kuo; Kuan-Ting Chen; Bo-Cheng Charles Lai (SiPS, 2013)

A distributed thread scheduler for dynamic multithreading on throughput processors. - Ta-Kan Yen; Hsien-Kai Kuo; Bo-Cheng Charles Lai (VLSI-DAT, 2013)

A learning-on-cloud power management policy for smart devices. - Gung-Yu Pan; Bo-Cheng Charles Lai; Sheng-Yen Chen; Jing-Yang Jou (ICCAD, 2014)

A Cache Aware Multithreading Decision Scheme on GPGPUs. - Ta Kang Yen; Bo Yao Yu; Bo-Cheng Charles Lai (MCSoC, 2014)

Automatic Data Layout Transformation for Heterogeneous Many-Core Systems. - Ying-Yu Tseng; Yu-Hao Huang; Bo-Cheng Charles Lai; Jiun-Liang Lin (NPC, 2014)

Reducing Contention in Shared Last-Level Cache for Throughput Processors. - Hsien-Kai Kuo; Bo-Cheng Charles Lai; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2014)

Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors. - Gung-Yu Pan; Jing-Yang Jou; Bo-Cheng Lai (ACM Trans. Design Autom. Electr. Syst., 2014)

Computation and Communication Aware task graph Scheduling on multi-GPU systems. - Yun-Ting Wang; Jia-Ying Lee; Bo-Cheng Charles Lai (DSP, 2015)

Design of Application Specific Throughput Processor for Matrix Operations. - Ping-Ju Wu; Chien-Yu Lin; Bo-Cheng Charles Lai (NBiS, 2015)

BRAM efficient multi-ported memory on FPGA. - Jiun-Liang Lin; Bo-Cheng Charles Lai (VLSI-DAT, 2015)

Power-Efficient Instancy Aware DRAM Scheduling. - Gung-Yu Pan; Chih-Yen Lai; Jing-Yang Jou; Bo-Cheng Charles Lai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Self adaptable multithreaded object detection on embedded multicore systems. - Bo-Cheng Charles Lai; Kun-Chun Li; Guan-Ru Li; Chih-Hsuan Chiang (J. Parallel Distributed Comput., 2015)

A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs. - Bo-Cheng Charles Lai; Hsien-Kai Kuo; Jing-Yang Jou (IEEE Trans. Computers, 2015)

Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors. - Gung-Yu Pan; Jed Yang; Jing-Yang Jou; Bo-Cheng Charles Lai (ACM Trans. Embed. Comput. Syst., 2015)

A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems. - Bo-Cheng Charles Lai; Kuan-Ting Chen; Ping-Ru Wu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Enhancing Data Reuse in Cache Contention Aware Thread Scheduling on GPGPU. - Chin-Fu Lu; Hsien-Kai Kuo; Bo-Cheng Charles Lai (CISIS, 2016)

A Quantitative Method to Data Reuse Patterns of SIMT Applications. - Bo-Cheng Charles Lai; Luis Garrido Platero; Hsien-Kai Kuo (IEEE Comput. Archit. Lett., 2016)

Unified Designs for High Performance LDPC Decoding on GPGPU. - Bo-Cheng Charles Lai; Chia-Ying Lee; Tsou-Han Chiu; Hsien-Kai Kuo; Chun-Kai Chang (IEEE Trans. Computers, 2016)

A Hadoop-based Principle Component Analysis on embedded heterogeneous platform. - Sheng-Yen Chen; Chia-I Wei; Yu-Chen Chiu; Bo-Cheng Charles Lai (VLSI-DAT, 2017)

An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA. - Bo-Cheng Charles Lai; Kun-Hua Huang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient Designs of Multiported Memory on FPGA. - Bo-Cheng Charles Lai; Jiun-Liang Lin (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks. - Chien-Yu Lin; Bo-Cheng Lai (ASP-DAC, 2018)

Towards high performance data analytic on heterogeneous many-core systems: A study on Bayesian Sequential Partitioning. - Bo-Cheng Lai; Tung-Yu Wu; Tsou-Han Chiu; Kun-Chun Li; Chia-Ying Lee; Wei-Chen Chien; Wing Hung Wong (J. Parallel Distributed Comput., 2018)

DP2: A Highly Parallel Range Join for Genome Analysis on Distributed Computing Platform. - Aman Sinha; Bo-Cheng Lai (HPCS, 2019)

Efficient Write Scheme for Algorithm-Based Multi-Ported Memory. - Bo-Ya Chen; Bo-En Chen; Bo-Cheng Lai (VLSI-DAT, 2019)

Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks. - Bo-Cheng Lai; Jyun-Wei Pan; Chien-Yu Lin (IEEE Trans. Very Large Scale Integr. Syst., 2019)

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. - Hung-Ming Chen; Chia-Lin Hu; Kang-Yu Chang; Alexandra Küster; Yu-Hsien Lin; Po-Shen Kuo; Wei-Tung Chao; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ICCAD, 2020)

A Two-Directional BigData Sorting Architecture on FPGAs. - Bo-Cheng Lai; Chun-Yen Chen; Yi-Da Hsin; Bo-Yen Lin (IEEE Comput. Archit. Lett., 2020)

Dataflow and microarchitecture co-optimisation for sparse CNN on distributed processing element accelerator. - Duc-An Pham; Bo-Cheng Lai (IET Circuits Devices Syst., 2020)

Selective bypassing and mapping for heterogeneous applications on GPGPUs. - Moustafa Emara; Bo-Cheng Lai (J. Parallel Distributed Comput., 2020)

A Novel Smart Assistance System for Blood Vessel Approaching: A Technical Report Based on Oximetry. - Chien-Ching Lee; Chia-Chun Chuang; Bo-Cheng Lai; Yi-Chia Huang; Jen-Yin Chen; Bor-Shyh Lin (Sensors, 2020)

REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory. - Bo-Cheng Lai; Bo-Ya Chen; Bo-En Chen; Yi-Da Hsin (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Parametric Study of Performance of Remote Photopletysmography System. - Edwin Arkel Rios; Chih-Chieh Lai; Bo-Rong Yan; Bo-Cheng Lai (ISCAS, 2021)

On Reconfiguring Memory-Centric AI Edge Devices for CIM. - Hung-Ming Chen; Cheng-En Ni; Kang-Yu Chang; Tzu-Chieh Chiang; Shih-Han Chang; Cheng-Yu Chiang; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ISOCC, 2021)

Reconfigurable Database Processor for Query Acceleration on FPGA. - Bo-En Chen; Bo-Yen Lin; Bo-Cheng Lai (VLSI-DAT, 2021)

DAF: re: A Challenging, Crowd-Sourced, Large-Scale, Long-Tailed Dataset For Anime Character Recognition. - Edwin Arkel Rios; Wen-Huang Cheng; Bo-Cheng Lai (CoRR, 2021)

Graph Neural Networks for Charged Particle Tracking on FPGAs. - Abdelrahman Elabd; Vesal Razavimaleki; Shi-Yu Huang; Javier M. Duarte; Markus Atkinson; Gage DeZoort; Peter Elmer; Jin-Xuan Hu; Shih-Chieh Hsu; Bo-Cheng Lai; Mark S. Neubauer; Isobel Ojalvo; et al. (CoRR, 2021)

DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. - Bo-Cheng Lai; Tzu-Chieh Chiang; Po-Shen Kuo; Wan-Ching Wang; Yan-Lin Hung; Hung-Ming Chen; Chien-Nan Liu; Shyh-Jye Jou (DATE, 2022)

A Highly Parallel Fine-Grained Sort-Merge Join on Near Memory Computing. - Po-Yen Lin; Yen-Shi Kuo; Bo-Cheng Lai (ISCAS, 2022)

Anime Character Recognition using Intermediate Features Aggregation. - Edwin Arkel Rios; Min-Chun Hu 001; Bo-Cheng Lai (ISCAS, 2022)

DLPrPPG: Development and Design of Deep Learning Platform for Remote Photoplethysmography. - Bo-Rong Yan; Edwin Arkel Rios; Wen-Hsien Lee; Bo-Cheng Lai (ISCAS, 2022)

MSIM: A Highly Parallel Near-Memory Accelerator for MinHash Sketch. - Aman Sinha; Jhih-Yong Mai; Bo-Cheng Lai (SOCC, 2022)

Distributed Sorting Architecture on Multiple FPGA. - Yi-Da Hsin; Yen-Shi Kuo; Bo-Cheng Lai (VLSI-DAT, 2022)

DSIM: Distributed Sequence Matching on Near-DRAM Accelerator for Genome Assembly. - Aman Sinha; Huei-Chun Yang; Pei-Yi Liu; Yen-Shi Kuo; Yuhao Fang; Tien-Shuo Chang; Ke-Han Li; Bo-Cheng Lai (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Graph Neural Networks for Charged Particle Tracking on FPGAs. - Abdelrahman Elabd; Vesal Razavimaleki; Shi-Yu Huang; Javier M. Duarte; Markus Atkinson; Gage DeZoort; Peter Elmer; Scott Hauck; Jin-Xuan Hu; Shih-Chieh Hsu; Bo-Cheng Lai; Mark S. Neubauer; et al. (Frontiers Big Data, 2022)

Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. - Shi-Yu Huang; Yun-Chen Yang; Yu-Ru Su; Bo-Cheng Lai; Javier M. Duarte; Scott Hauck; Shih-Chieh Hsu; Jin-Xuan Hu; Mark S. Neubauer (FPL, 2023)

REGAL: Reprogrammable Engines for Genome Analysis on LPDDR4x-based Stacked DRAM. - Aman Sinha; Yuhao Fang; Bo-Cheng Lai (ISCAS, 2023)

GRONA : A Framework for Gather-and-Reduce On Near-Memory Accelerators. - Aman Sinha; Pei-Yi Liu; Yuhao Fang; Jhih-Yong Mai; Bo-Cheng Lai (MCSoC, 2023)

A Bin-Based Indexing for Scalable Range Join on Genomic Data. - Aman Sinha; Bo-Cheng Lai; Jhih-Yong Mai (IEEE ACM Trans. Comput. Biol. Bioinform., 2023)

HeteroEML: Heterogeneous Design Methodology of Edge Machine Learning on CPU+FPGA Platform. - Yi-Ting Wu; Tzu-Yun Yen; Yu-Pei Lin; Bo-Cheng Lai (AICAS, 2024)

Automated Optimization for FPGA-Based Sonar Object Recognition Systems. - Pin-Hao Tung; Geng-Shi Jeng; Bo-Cheng Lai; Yu-Xiang Hung (APCCAS, 2024)

Down-Sampling Inter-layer Adapter for Parameter and Computation Efficient Ultra-Fine-Grained Image Recognition. - Edwin Arkel Rios; Femiloye Oyerinde; Min-Chun Hu 001; Bo-Cheng Lai (ECCV Workshops (11), 2024)

Near-DRAM Accelerated Matrix Multiplications. - Aman Sinha; Bo-Cheng Lai (MCSoC, 2024)

Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. - Bo-Han Li; Kuan-Chih Lin; Hao Zuo; Po-Cheng Pan; Hung-Ming Chen; Shyh-Jye Jou; Chien-Nan Jimmy Liu; Bo-Cheng Lai (MWSCAS, 2024)

FPGA Deployment of LFADS for Real-time Neuroscience Experiments. - Xiaohan Liu; Chi-Jui Chen; YanLun Huang; LingChi Yang; Elham E Khoda; Yihui Chen; Scott Hauck; Shih-Chieh Hsu; Bo-Cheng Lai (CoRR, 2024)

BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on an FPGA. - LingChi Yang; Chi-Jui Chen; Trung Le 002; Bo-Cheng Lai; Scott Hauck; Shih-Chieh Hsu (FPGA, 2025)

HiGTR: High-Performance FPGA Implementation of Complete GNN-based Trajectory Reconstruction for HEP. - Yun-Chen Yang; Hsuan-Wei Yu; Bo-Cheng Lai; Shih-Chieh Hsu; Mark S. Neubauer; Santosh Parajuli (FPGA, 2025)

Cross-Layer Cache Aggregation for Token Reduction in Ultra-Fine-Grained Image Recognition. - Edwin Arkel Rios; Jansen Christopher Yuanda; Vincent Leon Ghanz; Cheng-Wei Yu; Bo-Cheng Lai; Min-Chun Hu 001 (ICASSP, 2025)

Global-Local Similarity for Efficient Fine-Grained Image Recognition with Vision Transformers. - Edwin Arkel Rios; Min-Chun Hu 001; Bo-Cheng Lai (ISCAS, 2025)

Multi-dimensional Range Joins on HBM-enabled FPGAs. - Aman Sinha; Shih-Chen Lo; Bo-Cheng Lai (ISCAS, 2025)

Building Machine Learning Challenges for Anomaly Detection in Science. - Elizabeth G. Campolongo; Yuan-Tang Chou; Ekaterina Govorkova; Wahid Bhimji; Wei-Lun Chao; Chris Harris; Shih-Chieh Hsu; Hilmar Lapp; Mark S. Neubauer; Josephine M. Namayanja; Aneesh Subramanian; Philip C. Harris; et al. (CoRR, 2025)

Fine-Grained Image Recognition from Scratch with Teacher-Guided Data Augmentation. - Edwin Arkel Rios; Fernando Mikael; Oswin Gosal; Femiloye Oyerinde; Hao-Chun Liang; Bo-Cheng Lai; Min-Chun Hu 001 (CoRR, 2025)