A Unified Interconnects Testing Scheme for 3D Integrated Circuits. - Chih-Yun Pai; Ruei-Ting Gu; Bo-Chuan Cheng; Liang-Bi Chen; Katherine Shu-Min Li (Asian Test Symposium, 2011)

Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits. - Yi-Xue Zheng; Po-Ping Kan; Liang-Bi Chen; Kai-Yang Hsieh; Bo-Chuan Cheng; Katherine Shu-Min Li (SoCC, 2011)

De Bruijn graph-based communication modeling for fault tolerance in smart grids. - Bo-Chuan Cheng; Katherine Shu-Min Li; Sying-Jyan Wang (APCCAS, 2012)

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. - Katherine Shu-Min Li; Cheng-You Ho; Ruei-Ting Gu; Sying-Jyan Wang; Yingchieh Ho; Jiun-Jie Huang; Bo-Chuan Cheng; An-Ting Liu (Asian Test Symposium, 2013)

Optimized Pre-bond Test Methodology for Silicon Interposer Testing. - Katherine Shu-Min Li; Sying-Jyan Wang; Jia-Lin Wu; Cheng-You Ho; Yingchieh Ho; Ruei-Ting Gu; Bo-Chuan Cheng (ATS, 2014)

An efficient fault tolerance path finding algorithm for improving the robustness of multichannel wireless mesh networks. - Liang-Bi Chen; Bo-Chuan Cheng; You-Chiun Wang; Katherine Shu-Min Li; Jing-Jou Tang (ICCE, 2016)

Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis. - Katherine Shu-Min Li; Sying-Jyan Wang; Ruei-Ting Gu; Bo-Chuan Cheng (IEEE Des. Test, 2017)