Energy-delay minimization in nanoscale domino logic. - Bo Fu 002; Qiaoyan Yu; Paul Ampadu (ACM Great Lakes Symposium on VLSI, 2006)

Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing. - Bo Fu 002; Paul Ampadu (ICECS, 2006)

Techniques for robust energy efficient subthreshold domino CMOS circuits. - Bo Fu 002; Paul Ampadu (ISCAS, 2006)

Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency. - Bo Fu 002; Paul Ampadu (ISCAS, 2007)

A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects. - Bo Fu 002; Paul Ampadu (NanoNet, 2008)

A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes. - Bo Fu 002; Paul Ampadu (SoCC, 2008)

An Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes. - Bo Fu 002; Paul Ampadu (VLSI Design, 2008)

Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects. - Bo Fu 002; Paul Ampadu (DFT, 2009)

Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links. - Bo Fu 002; David Wolpert 001; Paul Ampadu (NOCS, 2009)

On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects. - Bo Fu 002; Paul Ampadu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n. - Bo Fu 002; Paul Ampadu (J. Signal Process. Syst., 2009)

Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design. - David Wolpert 001; Bo Fu 002; Paul Ampadu (NOCS, 2010)

Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects. - Bo Fu 002; Paul Ampadu (IET Comput. Digit. Tech., 2010)

Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction. - Bo Fu 002; Paul Ampadu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Adaptive Voltage Control for Energy-Efficient NoC Links. - Paul Ampadu; Bo Fu 002; David Wolpert 001; Qiaoyan Yu (Low Power Networks-on-Chip, 2011)