A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. - Bo Jiao 003; Jinshan Zhang 006; Yuanyuan Xie; Shunli Wang 001; Haozhe Zhu; Xiaoyang Kang 001; Zhiyan Dong; Lihua Zhang 002; Chixiao Chen (ASP-DAC, 2021)

Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. - Bo Jiao 003; Haozhe Zhu; Jinshan Zhang 006; Shunli Wang 001; Xiaoyang Kang 001; Lihua Zhang 002; Mingyu Wang 001; Chixiao Chen (ACM Great Lakes Symposium on VLSI, 2021)

ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. - Jinshan Zhang 006; Bo Jiao 003; Yunzhengmao Wang; Haozhe Zhu; Lihua Zhang 002; Chixiao Chen (ACM Great Lakes Symposium on VLSI, 2021)

CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space. - Shunli Wang 001; Shuaibing Wang; Bo Jiao 003; Dingkang Yang; Liuzhen Su; Peng Zhai; Chixiao Chen; Lihua Zhang 002 (IROS, 2022)

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. - Haozhe Zhu; Bo Jiao 003; Jinshan Zhang 006; Xinru Jia; Yunzhengmao Wang; Tianchan Guan; Shengcheng Wang; Dimin Niu; Hongzhong Zheng; Chixiao Chen; Mingyu Wang 001; Lihua Zhang 002; et al. (ISSCC, 2022)

A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. - Jie Liao; Bo Jiao 003; Jinshan Zhang 006; Shiwei Liu 002; Hao Jiang 024; Jun Tao 001; Wenning Jiang; Qi Liu 010; Lihua Zhang 002; Haozhe Zhu; Chixiao Chen (ISCAS, 2023)

A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer. - Chen Mu; Zhirui Huang; Hao Jiang 024; Jie Liao; Bo Jiao 003; Yuliang Zhou; Haozhe Zhu; Jianguo Yang; Qi Liu 010; Chixiao Chen (A-SSCC, 2024)

FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer. - Bo Jiao 003; Lei Xu; Xinyu Yu; Haitao Yang; Haozhe Zhu; Yu Wang; Jundong Zhu; Dexin Wen; Lingli Wang; Jun Tao 001; Chixiao Chen; Yinhe Han 001; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet System. - Siqi He; Haozhe Zhu; Jiapei Zheng; Lizhou Wu; Bo Jiao 003; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (DAC, 2025)

EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer. - Siyao Jia; Bo Jiao 003; Haozhe Zhu; Chixiao Chen; Qi Liu 010; Ming Liu 022 (HPCA, 2025)

37.4 SHINSAI: A 586mm2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory. - Bo Jiao 003; Haozhe Zhu; Yuman Zeng; Yongjiang Li; Jie Liao; Siyao Jia; Mochen Tian; Zexing Chen; Jundong Zhu; Dexin Wen; Yan Wang; Yu Wang 046; et al. (ISSCC, 2025)